Survey on Formal Verification Methods for Digital IC

This paper presents a survey of the state-of-art of formal verification technique. The expression models for formal verification are introduced and analyzed. The characteristics of each model are expounded. Moreover, the typical model checking techniques are studied. Equivalence checking and property checking are introduced. The development trend for formal verification is discussed.

[1]  Axel Jantsch,et al.  System level verification of digital signal processing applications based on the polynomial abstraction technique , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[2]  Armin Biere,et al.  A survey of recent advances in SAT-based formal verification , 2005, International Journal on Software Tools for Technology Transfer.

[3]  Priyank Kalla,et al.  Simulation Bounds for Equivalence Verification of Arithmetic Datapaths with Finite Word-Length Operands , 2006, 2006 Formal Methods in Computer Aided Design.

[4]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[5]  Zhihong Zeng,et al.  Taylor expansion diagrams: a compact, canonical representation with applications to symbolic verification , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[6]  Dhiraj K. Pradhan,et al.  Mathematical framework for representing discrete functions as word-level polynomials , 2003, Eighth IEEE International High-Level Design Validation and Test Workshop.

[7]  Pallab Dasgupta,et al.  Abstraction of word-level linear arithmetic functions from bit-level component descriptions , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[8]  Sharad Malik,et al.  Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[9]  Priyank Kalla,et al.  Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[10]  Priyank Kalla,et al.  Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs , 2006, IEEE Transactions on Computers.

[11]  Armin Biere,et al.  Bounded Model Checking Using Satisfiability Solving , 2001, Formal Methods Syst. Des..

[12]  Niklas Sörensson,et al.  Temporal induction by incremental SAT solving , 2003, BMC@CAV.

[13]  Eugene Goldberg,et al.  BerkMin: A Fast and Robust Sat-Solver , 2002, Discret. Appl. Math..

[14]  Kurt Keutzer,et al.  Functional vector generation for HDL models using linear programming and 3-satisfiability , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[15]  Jinzhao Wu,et al.  Application of Wu's method to symbolic model checking , 2005, ISSAC.

[16]  Rolf Drechsler,et al.  RTL-datapath verification using integer linear programming , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[17]  Zhihong Zeng,et al.  LPSAT: a unified approach to RTL satisfiability , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[18]  Robert K. Brayton,et al.  Using SAT for combinational equivalence checking , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[19]  Giovanni De Micheli,et al.  Application of symbolic computer algebra in high-level data-flow synthesis , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Priyank Kalla,et al.  Equivalence verification of arithmetic datapaths with multiple word-length operands , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[21]  Andreas Kuehlmann,et al.  Equivalence checking using cuts and heaps , 1997, DAC.

[22]  Yusuke Matsunaga.  An efficient equivalence checker for combinational circuits , 1996, DAC '96.

[23]  Pablo Sanchez,et al.  Assertion checking of behavioral descriptions with nonlinear solver , 2005, 2005 International Conference on Computer Design.

[24]  Giovanni De Micheli,et al.  Polynomial circuit models for component matching in high-level synthesis , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[25]  Rolf Drechsler,et al.  Using Word-Level Information in Formal Hardware Verification , 2004 .

[26]  Alexandru Nicolau,et al.  Expression equivalence checking using interval analysis , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.