Chapter Four – Nanoscale FETs

Since the invention of the integrated circuit (IC) in 1958, engineers and researchers around the world have worked on how to put more speed, performance and value onto smaller chips of silicon. The semiconductor industry has made considerable progress, especially regarding the Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The fundamental driver has been the continued shrinking of its feature sizes, allowing the exponential growth in device count that tracks the well-known Moore's Law, first formulated by Intel co-founder Gordon Moore. However, this law is a rough prediction of the future of IC expansion. The need of a more accurate forecast defined the International Technology Roadmap for Semiconductors (ITRS), which has been predicting and driving the pace of semiconductor technology at the same time. The use of CMOS technology also for high-frequency (HF) applications is now common. This is due to the significant increase in the unity current gain frequency of modern deep submicrometer MOS devices. However, to be competitive against other technologies for high-frequency (HF) applications, MOSFETs need to demonstrate comparable noise performance. Although the channel thermal noise of MOSFET has been known to be the most dominant source of noise in the device, additional noise sources emerge as the CMOS technology scales down, such as gate tunneling current, and substrate noise. On the other hand, since the noise figure of the MOSFET decreases with technology scaling, HF noise measurement, and characterization of extremely small devices is becoming more challenging. Due to these challenges, there is a lot of research around new technologies, new materials and new devices. This chapter presents a review of some of the recent results in this exciting area.

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