Hybrid instruction cache partitioning for preemptive real-time systems

Cache memories have been historically avoided in real-time systems because of their unpredictable behavior. In addition to the research focused at obtaining the worst-case execution time of cached programs (typically assuming no preemption), some techniques have been presented to deal with the cache interference due to preemptions (extrinsic or inter-task cache interference). These techniques either account for the extrinsic (cache) interference in the schedulability analysis, or annuls it by partitioning the cache. This paper describes a new technique, hybrid partitioning, which is a mixture of the former two. It either provides a task with a private partition or accounts for the extrinsic interference that may arise. The hybrid technique outperforms the original two for any workload or hardware configuration. In conclusion, it represents a powerful yet general framework for dealing with extrinsic cache interference.

[1]  Alan Burns,et al.  The Olympus Attitude and Orbital Control System: A Case Study in Hard Real-Time System Design and Implementation , 1993, Ada-Europe.

[2]  André Seznec,et al.  A case for two-way skewed-associative caches , 1993, ISCA '93.

[3]  Jay K. Strosnider,et al.  A Dynamic Programming Algorithm for Cache/Memory Partitioning for Real-Time Systems , 1993, IEEE Trans. Computers.

[4]  Jay K. Strosnider,et al.  SMART (strategic memory allocation for real-time) cache design using the MIPS R3000 , 1990, [1990] Proceedings 11th Real-Time Systems Symposium.

[5]  D. B. Kirk,et al.  SMART (strategic memory allocation for real-time) cache design , 1989, [1989] Proceedings. Real-Time Systems Symposium.

[6]  Lui Sha,et al.  An Optimal Priority Inheritance Protocol for Real-Time Synchronization , 1988 .

[7]  Frank Mueller,et al.  Compiler support for software-based cache partitioning , 1995, Workshop on Languages, Compilers, & Tools for Real-Time Systems.

[8]  Kelvin D. Nilsen.  Real-time is no longer a small specialized niche , 1995, Proceedings 5th Workshop on Hot Topics in Operating Systems (HotOS-V).

[9]  Alan Jay Smith,et al.  Evaluating Associativity in CPU Caches , 1989, IEEE Trans. Computers.

[10]  Sang Lyul Min,et al.  An accurate worst case timing analysis technique for RISC processors , 1994, 1994 Proceedings Real-Time Systems Symposium.

[11]  David B. Whalley,et al.  Integrating the timing analysis of pipelining and instruction caching , 1995, Proceedings 16th IEEE Real-Time Systems Symposium.

[12]  Lui Sha,et al.  Priority Inheritance Protocols: An Approach to Real-Time Synchronization , 1990, IEEE Trans. Computers.

[13]  Jyh-Charn Liu,et al.  Deterministic upperbounds of the worst-case execution times of cached programs , 1994, 1994 Proceedings Real-Time Systems Symposium.

[14]  Andy J. Wellings,et al.  Adding instruction cache effect to schedulability analysis of preemptive real-time systems , 1996, Proceedings Real-Time Technology and Applications.

[15]  Lee Higbee.  Quick and easy cache performance analysis , 1990, CARN.

[16]  David B. Kirk,et al.  Process dependent static cache partitioning for real-time systems , 1988, Proceedings. Real-Time Systems Symposium.

[17]  Frank Mueller.  Compiler support for software-based cache partitioning , 1995 .

[18]  Alan Burns,et al.  Preemptive priority-based scheduling: an appropriate engineering approach , 1995 .

[19]  Alan Burns,et al.  STRESS: A simulator for hard real‐time systems , 1994, Softw. Pract. Exp..

[20]  Sharad Malik,et al.  Efficient microarchitecture modeling and path analysis for real-time software , 1995, Proceedings 16th IEEE Real-Time Systems Symposium.

[21]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[22]  Chang-Gun Lee,et al.  Enhanced analysis of cache-related preemption delay in fixed-priority preemptive scheduling , 1996, Proceedings Real-Time Systems Symposium.

[23]  Jay K. Strosnider,et al.  Allocating SMART cache segments for schedulability , 1991 .

[24]  David B. Whalley,et al.  Bounding worst-case instruction cache performance , 1994, 1994 Proceedings Real-Time Systems Symposium.

[25]  Andy J. Wellings,et al.  Adding instruction cache effect to an exact schedulability analysis of preemptive real-time systems , 1996, Proceedings of the Eighth Euromicro Workshop on Real-Time Systems.

[26]  Kelvin D. Nilsen,et al.  Cache Issues in Real-Time Systems , 1994 .

[27]  C. Douglas Locke,et al.  Building a predictable avionics platform in Ada: a case study , 1991, [1991] Proceedings Twelfth Real-Time Systems Symposium.

[28]  John P. Lehoczky,et al.  An experimental investigation of synchronization protocols , 1989 .

[29]  Sang Lyul Min,et al.  Analysis of cache-related preemption delay in fixed-priority preemptive scheduling , 1998, 17th IEEE Real-Time Systems Symposium.

[30]  Chang-Gun Lee,et al.  Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemtive Scheduling , 1998, IEEE Trans. Computers.

[31]  Andrew Wolfe,et al.  Software-based cache partitioning for real-time applications , 1994 .

[32]  Kuninori Kimotsuki,et al.  THE KEY-NOTE , 1991 .