BIST vs. ATE: need a different vehicle?

Ask ASIC designers whether they plan to use BIST, and the answer will depend on whether the designer has seen the 'swamp' of test complexity for deep submicron ICs. With gate counts >500 K and internal clock rates >200 MHz, test costs can equal silicon costs unless embedded test facilities are used. For these ICs, which are quickly becoming mainstream, which functions are best tested with BIST? An attempt is made to answer this question, and it is concluded that, compared to external ATE, BIST can be more effective for testing multiple embedded memories, high speed random logic, and some mixed-signal functions. It is recommended that designers and test engineers should anticipate the approaching swamp of test complexity and decreasing test yields.