Cache design trade-offs for power and performance optimization: a case study
暂无分享,去创建一个
[1] Alvin M. Despain,et al. Branch with masked squashing in superpipelined processors , 1994, ISCA '94.
[2] Norman P. Jouppi,et al. WRL Research Report 93/5: An Enhanced Access and Cycle Time Model for On-chip Caches , 1994 .
[3] Peter Van Roy,et al. High-performance logic programming with the Aquarius Prolog compiler , 1992, Computer.
[4] Bradley G. Burgess,et al. The PowerPC 603 microprocessor: a high performance, low power, superscalar RISC microprocessor , 1994, Proceedings of COMPCON '94.
[5] Alvin M. Despain,et al. Cache designs for energy efficiency , 1995, Proceedings of the Twenty-Eighth Annual Hawaii International Conference on System Sciences.
[6] Alan Jay Smith,et al. A Comparative Study of Set Associative Memory Mapping Algorithms and Their Use for Cache and Main Memory , 1978, IEEE Transactions on Software Engineering.
[7] Chi-Ying Tsui,et al. Saving power in the control path of embedded processors , 1994, IEEE Design & Test of Computers.
[8] N. Jouppi,et al. Tradeoffs in two-level on-chip caching , 1994, Proceedings of 21 International Symposium on Computer Architecture.
[9] Mark D. Hill,et al. A case for direct-mapped caches , 1988, Computer.
[10] T. Wada,et al. An analytical access time model for on-chip cache memories , 1992 .
[11] Ralph Haygood. A Prolog Benchmark Suite for Aquarius , 1989 .