Exploring the Design Space for Crossbar Arrays Built With Mixed-Ionic-Electronic-Conduction (MIEC) Access Devices
暂无分享,去创建一个
Pritish Narayanan | Kumar Virwani | Kailash Gopalakrishnan | Alvaro Padilla | Geoffrey W. Burr | Rohit S. Shenoy | Samantha Stephens | Bulent N. Kurdi | K. Gopalakrishnan | P. Narayanan | G. Burr | R. Shenoy | K. Virwani | A. Padilla | B. Kurdi | S. Stephens
[1] H.-S. Philip Wong,et al. Effect of Wordline/Bitline Scaling on the Performance, Energy Consumption, and Reliability of Cross-Point Memory Array , 2013, JETC.
[2] An Chen,et al. Accessibility of nano-crossbar arrays of resistive switching devices , 2011, 2011 11th IEEE International Conference on Nanotechnology.
[3] Masahide Matsumoto,et al. A 130.7mm2 2-layer 32Gb ReRAM memory device in 24nm technology , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[4] Udayan Ganguly,et al. The Impact of n-p-n Selector-Based Bipolar RRAM Cross-Point on Array Performance , 2013, IEEE Transactions on Electron Devices.
[5] Chang Hua Siau,et al. Low power cross-point memory architecture , 2011, IEEE Asian Solid-State Circuits Conference 2011.
[6] Tuo-Hung Hou,et al. Dependence of Read Margin on Pull-Up Schemes in High-Density One Selector–One Resistor Crossbar Array , 2013, IEEE Transactions on Electron Devices.
[7] Chang Hua Siau,et al. A 0.13µm 64Mb multi-layered conductive metal-oxide memory , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).
[8] G. W. Burr,et al. Recovery dynamics and fast (sub-50ns) read operation with Access Devices for 3D crosspoint memory based on mixed-ionic-electronic-conduction (MIEC) , 2013, 2013 Symposium on VLSI Technology.
[9] Guido Groeseneken,et al. Selector design considerations and requirements for 1 SIR RRAM crossbar array , 2014, 2014 IEEE 6th International Memory Workshop (IMW).
[10] G. Burr,et al. Highly-scalable novel access device based on Mixed Ionic Electronic conduction (MIEC) materials for high density phase change memory (PCM) arrays , 2010, 2010 Symposium on VLSI Technology.
[11] Y. S. Kim,et al. Integration of 4F2 selector-less crossbar array 2Mb ReRAM based on transition metal oxides for high density memory applications , 2012, 2012 Symposium on VLSI Technology (VLSIT).
[12] R. Waser,et al. A Fundamental Analysis of Nano-Crossbars with Non-Linear Switching Materials and its Impact on TiO2 as a Resistive Layer , 2008, 2008 8th IEEE Conference on Nanotechnology.
[13] T.G. Noll,et al. Fundamental analysis of resistive nano-crossbars for the use in hybrid Nano/CMOS-memory , 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.
[14] Cong Xu,et al. Design trade-offs for high density cross-point resistive memory , 2012, ISLPED '12.
[15] Guido Groeseneken,et al. Analysis of the effect of cell parameters on the maximum RRAM array size considering both read and write , 2012, 2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC).
[16] Jiale Liang,et al. An Ultra-Low Reset Current Cross-Point Phase Change Memory With Carbon Nanotube Electrodes , 2012, IEEE Transactions on Electron Devices.
[17] H.-S. Philip Wong,et al. Size limitation of cross-point memory array and its dependence on data storage pattern and device parameters , 2010, 2010 IEEE International Interconnect Technology Conference.
[18] Jiale Liang,et al. Cross-Point Memory Array Without Cell Selectors—Device Characteristics and Data Storage Pattern Dependencies , 2010, IEEE Transactions on Electron Devices.
[19] Winfried W. Wilcke,et al. Storage-class memory: The next storage system technology , 2008, IBM J. Res. Dev..
[20] Bing Chen,et al. RRAM Crossbar Array With Cell Selection Device: A Device and Circuit Interaction Study , 2013, IEEE Transactions on Electron Devices.
[21] Yukio Hayakawa,et al. An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput , 2012, IEEE Journal of Solid-State Circuits.
[22] Tuo-Hung Hou,et al. On the potential of CRS, 1D1R, and 1S1R crossbar RRAM for storage-class memory , 2013, 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).
[23] K. Gopalakrishnan,et al. Large-scale (512kbit) integration of multilayer-ready access-devices based on mixed-ionic-electronic-conduction (MIEC) at 100% yield , 2012, 2012 Symposium on VLSI Technology (VLSIT).
[24] Pritish Narayanan,et al. Access devices for 3 D crosspoint memorya ) , 2014 .
[25] Tuo-Hung Hou,et al. Bipolar Nonlinear $\hbox{Ni/TiO}_{2}\hbox{/}\hbox{Ni}$ Selector for 1S1R Crossbar Array Applications , 2011, IEEE Electron Device Letters.
[26] An Chen,et al. A Comprehensive Crossbar Array Model With Solutions for Line Resistance and Nonlinear Device Characteristics , 2013, IEEE Transactions on Electron Devices.
[27] P. Narayanan,et al. Exploring the design space for resistive nonvolatile memory crossbar arrays with mixed ionic-electronic-conduction (MIEC)-based Access Devices , 2014, 72nd Device Research Conference.
[28] Cheol Seong Hwang,et al. A theoretical model for Schottky diodes for excluding the sneak current in cross bar array resistive memory , 2010, Nanotechnology.
[29] M. Breitwisch,et al. Endurance and scaling trends of novel access-devices for multi-layer crosspoint-memory based on mixed-ionic-electronic-conduction (MIEC) materials , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.
[30] Kailash Gopalakrishnan,et al. Overview of candidate device technologies for storage-class memory , 2008, IBM J. Res. Dev..
[31] P. Narayanan,et al. Access devices for 3D crosspoint memorya) , 2014 .
[32] Narayan Srinivasa,et al. A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications. , 2012, Nano letters.
[33] L. Goux,et al. Dynamic ‘hour glass’ model for SET and RESET in HfO2 RRAM , 2012, 2012 Symposium on VLSI Technology (VLSIT).
[34] Pritish Narayanan,et al. MIEC (mixed-ionic-electronic-conduction)-based access devices for non-volatile crossbar memory arrays , 2014 .
[35] K. Virwani,et al. Sub-30nm scaling and high-speed operation of fully-confined Access-Devices for 3D crosspoint memory based on mixed-ionic-electronic-conduction (MIEC) materials , 2012, 2012 International Electron Devices Meeting.
[36] Kuk-Hwan Kim,et al. Crossbar RRAM Arrays: Selector Device Requirements During Read Operation , 2014, IEEE Transactions on Electron Devices.
[37] Pritish Narayanan,et al. Circuit-level benchmarking of access devices for resistive nonvolatile memory arrays , 2014 .