A PRML read/write channel IC using analog signal processing for 200 Mb/s HDD
暂无分享,去创建一个
K. Parsi | R. P. Burns | A. Chaiken | M. J. Chambers | W. R. Forni | David B. Harnishfeger | S. Kaylor | M. J. Pennell | J. O. Perez | N. Rao | M. Rohrbaugh | M. Ross | G. L. Stuhlmiller
[1] Robert Andrew Kertis,et al. A 16 MB/s PRML read/write data channel , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.
[2] C. Richard Johnson,et al. Sign-sign LMS convergence with independent stochastic inputs , 1990, IEEE Trans. Inf. Theory.
[3] Roy D. Cideciyan,et al. A PRML System for Digital Magnetic Recording , 1992, IEEE J. Sel. Areas Commun..
[4] H. Wallinga,et al. A CMOS analog continuous-time delay line with adaptive delay-time control , 1988 .
[5] Masaki Ishida,et al. A 10-b 100-Msample/s pipelined subranging BiCMOS ADC , 1993 .
[6] D. Browning,et al. A 72 Mb/s PRML disk-drive channel chip with an analog sampled-data signal processor , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.