Low-Power and High Performance Sinusoidal Clocked Dynamic Circuit Design

Important characteristic of any VLSI circuit is its power consumption, reliability, operating speed and silicon area. Dynamic CMOS designs provide high operating speeds compared to static CMOS designs combined with low silicon area requirements. Pipelines can be used for achieving high circuit operating speeds. However, as the operating frequency increases, the number of pipeline stages should also increase and so the memory elements. These memory elements increase the area overhead and restrict the maximum achievable frequency due to their delays. Memory-less pipelines based on dynamic design address these issues but, still require high power consumption for the clock signal. In this paper we propose a sinusoidal three-phase clocking scheme that reduces the power required by the clock and offers high circuit operating frequencies. Thus the proposed technique provides advantages over preexisting techniques in terms of power requirement, area of implementation and operating speed.

[1]  Samuel D. Naffziger,et al.  The implementation of the Itanium 2 microprocessor , 2002, IEEE J. Solid State Circuits.

[2]  Spiridon Nikolaidis,et al.  Low-power/low-swing domino CMOS logic , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[3]  C.A.T. Salama,et al.  Charge redistribution and noise margins in domino CMOS logic , 1986 .

[4]  E. You,et al.  A third-generation SPARC V9 64-b microprocessor , 2000, IEEE Journal of Solid-State Circuits.

[5]  Muhammad E. S. Elrabaa,et al.  A contention-free domino logic for scaled-down CMOS technologies with ultra low threshold voltages , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[6]  Christer Svensson,et al.  New domino logic precharged by clock and data , 1993 .

[7]  Harold S. Stone,et al.  A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.

[8]  Graham A. Jullien,et al.  Fast adders using enhanced multiple-output domino logic , 1997 .

[9]  D. Timmermann,et al.  Dynamic Circuit Techniques in Deep Submicron Technologies: Domino Logic reconsidered , 2006, 2006 IEEE International Conference on IC Design and Technology.

[10]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[11]  Yiorgos Tsiatouhas,et al.  The use of pre-evaluation phase in dynamic CMOS logic , 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

[12]  Yiorgos Tsiatouhas,et al.  Memory-Less Pipeline Dynamic Circuit Design Technique , 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

[13]  Yiorgos Tsiatouhas,et al.  High performance and low power dynamic circuit design , 2011, 2011 IEEE 9th International New Circuits and systems conference.

[14]  R. Krishnamurthy,et al.  A 9GHz 65nm Intel Pentium 4 Processor Integer Execution Core , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[15]  Ali Afzali-Kusha,et al.  Clock Delayed Domino Logic With Efficient Variable Threshold Voltage Keeper , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  David Harris,et al.  Skew-Tolerant Circuit Design , 2000 .

[17]  M.A. Horowitz,et al.  Skew-tolerant domino circuits , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[18]  Sung-Mo Kang,et al.  Improved domino structures effective for high performance design , 1999 .

[19]  Sanu Mathew,et al.  A 9-GHz 65-nm Intel® Pentium 4 Processor Integer Execution Unit , 2007, IEEE J. Solid State Circuits.

[20]  C. M. Files,et al.  A Mature Methodology for Implementing Multi-Valued Logic in Silicon , 2008, 38th International Symposium on Multiple Valued Logic (ismvl 2008).