Estimation of the weighted maximum switching activity in combinational CMOS circuits

To achieve high reliability in VLSI designs, estimation of the maximum power dissipation during the design cycle is becoming important. In previous work, it was shown that maximizing dissipation is equivalent to maximizing gate output activity, appropriately weighted to account for differing load capacitances. Recent advances in Boolean satisfiability (SAT) models and algorithms have made it tempting to use satisfiability-based techniques in solving various VLSI design-related problems such as verification and test generation. SAT solvers have also been extended to handle 0-1 integer linear programming (ILP) problems. In this paper, we present an ILP-based solution to compute the maximum weighted activity of combinational circuits. The problem is formulated as an ILP instance and the new SAT-based ILP solvers are used to find an estimate for the power dissipation. For performance comparison, the problem is also solved using generic ILP solvers. The validity of the proposed approach is demonstrated using benchmarks from the MCNC suite

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