A 1-V 5-MHz Bandwidth 68.3-dB SNDR Continuous-Time Delta-Sigma Modulator With a Feedback-Assisted Quantizer

A low-power continuous-time delta-sigma modulator (CTDSM) incorporating a multi-bit feedback-assisted quantizer (FBAQ) is presented in this paper. The proposed multi-bit quantizer is placed in a negative feedback loop to reduce the signal swing at its input. As a result, the number of comparator required for signal quantization is reduced. Furthermore, the modulator is optimized for low-voltage swing operation, in which the excess-loop-delay compensation is embedded without requiring additional hardware. With a 240-MHz sampling clock, this CTDSM achieves a peak SNDR of 68.3 dB and a dynamic range of 71 dB over a 5-MHz signal bandwidth. Fabricated in a 90-nm CMOS process, this chip consumes 4.6 mW from a 1-V supply, which corresponds to a figure of merit (FoM) of 216 fJ/conversion-step.

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