Advanced bipolar circuits

Advances in high-speed, low-power bipolar circuits aimed at achieving superior power-delay performance and load-driving capability over conventional ECL and NTL circuits are reviewed. The basic principles underlying power/speed improvement including charge-buffering, DC/AC-coupled active pull-down schemes, and complementary push-pull approaches, are examined. The utilization and combination of these basic principles to form various high-speed, low-power circuits in both n-p-n-only and complementary circuit configurations and the design tradeoffs of these circuits are discussed.<<ETX>>

[1]  M. Suzuki,et al.  A 50-ps 7 K-gate masterslice using mixed cells consisting of an NTL gate and an LCML macrocell , 1987 .

[2]  Ching-Te Chuang,et al.  A 23-ps/2.1-mW ECL gate with an AC-coupled active pull-down emitter-follower stage , 1989 .

[3]  D. D. Tang,et al.  High-Speed Low-Power AC-coupled Complementary Push-pull , 1991, 1991 Symposium on VLSI Circuits.

[4]  J.D. Cressler,et al.  A submicrometer high-performance bipolar technology , 1989, IEEE Electron Device Letters.

[5]  B. Coy,et al.  A 13000 gate 3 layer metal bipolar gate array , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[6]  Ching-Te Chuang NTL with complementary emitter-follower driver: a high-speed low-power push-pull logic circuit , 1990 .

[7]  M. Suzuki,et al.  Advanced 5K-gate bipolar gate array with a 267 ps basic gate delay , 1984, IEEE Journal of Solid-State Circuits.

[8]  S.K. Wiedmann Potential of bipolar complementary device/Circuit technology , 1987, 1987 International Electron Devices Meeting.

[9]  T.H. Ning,et al.  Sub-300-ps CBL circuits , 1989, IEEE Electron Device Letters.

[10]  Ching-Te Chuang,et al.  A high-speed low-power JFET pull-down ECL circuit , 1990, Proceedings on Bipolar Circuits and Technology Meeting.

[11]  C. M. Horwitz,et al.  Complementary current-mirror logic , 1988 .

[12]  M. Suzuki,et al.  A 5000-gate bipolar masterslice LSI with 500ps loaded gate delay , 1983, 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[13]  Ching-Te Chuang,et al.  A 23 ps/2.1 mW ECL gate , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

[14]  Ching-Te Chuang,et al.  High-speed low-power direct-coupled complementary push-pull ECL circuit , 1992 .

[15]  Ching-Te Chuang,et al.  High-speed low-power charge-buffered active-pull-down ECL circuit , 1990, Proceedings on Bipolar Circuits and Technology Meeting.

[16]  R.L. Treadway DC analysis of current mode logic , 1989, IEEE Circuits and Devices Magazine.

[17]  M. Usami,et al.  SPL (super push-pull logic) a bipolar novel low-power high-speed logic circuit , 1989, Symposium 1989 on VLSI Circuits.

[18]  S. K. Wiedmann Charge Buffered Logic (CBL) - A New Complementary Bipolar Circuit Concept , 1985, 1985 Symposium on VLSI Technology. Digest of Technical Papers.