A Graph-Based Spatial Mapping Algorithm for a Coarse Grained Reconfigurable Architecture Template

Coarse Grained Reconfigurable Arrays (CGRAs) have been more and more popular recently due to their high performance with low power consumption. An intelligent compiler is essential to execute applications on CGRAs effectively. However, automatically compilation for CGRAs still faces many challenges though many algorithms have been proposed. In this paper, we present an effective mapping algorithm which is targetable to a parameterized architecture template. The main contributions are an effective priority scheme, a satisfying backtracking algorithm and a fast control data flow graph (CDFG) splitting method. The experimental results demonstrate that our technique gains the performance very close to manual optimization.

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