Channel routing in Manhattan-diagonal model

This paper presents a new technique of channel routing based on the Manhattan-Diagonal (MD) model. The layout grid is assumed to consist of two layers with tracks in horizontal, vertical and /spl plusmn/45/spl deg/ directions. First, we consider the non-overlap model and present a simple O(l,d) time algorithm that routes an arbitrary channel with no cyclic vertical constraints in w tracks, where l is the length of the channel, d is the channel density, and d/spl les/w/spl les/(d+1). Next, we describe an output-sensitive algorithm that can route general channels with cyclic vertical constraints using w tracks, in O(l,w) time allowing overlapping of wiring segments in two layers. The router outputs an 18-track solution for the Deutsch's difficult example, a 2-track solution for Burstein's difficult channel, and a 15-track solution for cycle.tough without inserting any extra row or column. Apart from quick termination, the proposed algorithms provide solutions with significantly low via count and reduced wire length. The study thus reveals the superiority of MD-routing strategy to classical techniques.

[1]  Jason Cong,et al.  A layout modification approach to via minimization , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Fabrizio Luccio,et al.  A 2d channel router for the diagonal model , 1991, Integr..

[3]  Alberto Sangiovanni-Vincentelli,et al.  Chameleon: A New Multi-Layer Channel Router , 1986, DAC 1986.

[4]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[5]  S. Sitharama Iyengar,et al.  A general greedy channel routing algorithm , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  R.L. Rivest,et al.  A "Greedy" Channel Router , 1982, 19th Design Automation Conference.

[7]  Alberto L. Sangiovanni-Vincentelli,et al.  A New Symbolic Channel Router: YACR2 , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Takeshi Yoshimura,et al.  Efficient Algorithms for Channel Routing , 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Ronald L. Rivest,et al.  A "Greedy" Channel Router , 1982, DAC 1982.

[10]  Sudebkumar Prasant Pal,et al.  A general graph theoretic framework for multi-layer channel routing , 1995, Proceedings of the 8th International Conference on VLSI Design.

[11]  Peter Robinson,et al.  Channel routing by sorting , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Jason Cong,et al.  A new approach to three- or four-layer channel routing , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  R. Pelavin,et al.  Hierarchical channel router , 1988, 25 years of DAC.

[14]  Sudebkumar Prasant Pal,et al.  Computing area and wire length efficient routes for channels , 1995, Proceedings of the 8th International Conference on VLSI Design.

[15]  Fabrizio Luccio,et al.  Channel routing for strictly multiterminal nets , 1989, Integr..

[16]  Fabrizio Luccio,et al.  Routing in Times Square Mode , 1990, Inf. Process. Lett..