Hardware design of a motion video decoder for 1-1.5 Mbps rate applications

Abstract In this paper, we designed and evaluated the hardware complexity of a motion video decoder, the Bellcore proposed ISO-MPEG decoder for 1–1.5 Mbps rate applications. It is designed to perform the following features: (1) Forward normal/fast playback; (2) Reverse normal/fast playback; (3) Transcoding of CCITT RM8; (4) Transcoding of JPEG Baseline System; (5) Still image build up with high resolution; (6) Random access. The decoder is partitioned into functional modules such that the hardware components can be shared for performing different features. Besides using a commercially available IDCT chip, we designed a JPEG VLD module, a loop filter module, an inverse quantizer module, an address generator module and a format converter module. All the modules are RM8 and/or JPEG compatible. We also described the organization of frame memories and procedure for integrating all the modules to perform different tasks.