PLC 시스템을 위한 CMOS Analog Front-End 설계

This paper presents a Full-CMOS single-chip for Power Line Communication(PLC) systems. To achieve the low power operation and the low cost, the Analog Front-End is designed with Full-CMOS 0.25㎛ technology. In the Rx part, the Pre-Amp and Programmable Gain Amplifier (PGA) is designed to have a wide dynamic range and gain control range because the signal from the power line is variable depending on the distance. In the Tx part, the proposed Line Driver can drive the power line without external driving circuits composed of BJT and diode device. This chip is fabricated with 0.25㎛ CMOS technology, and the die area is 3.2㎜ × 3.2㎜. The power consumption is 25㎽ at 3.0V supply voltage in Rx mode, and 325㎽ at Tx mode, respectively.