Infrastructure IP for Programming and Test of in-system Memory Devices

Today’s efforts to reduce both system manufacturing costs and in-the-field in-system upgrades requires new flexible and cost effective methods of testing complex memories and programming non-volatile memories. FLASH memory, Serial EEPROM, SDRAM, NAND memory, FCRAM and DDRRAM, all present problems for efficient in-system programming and test in systems with limited physical access. Reduced contact methods based on IEEE 1149.1 for testing PCBs and Systems rely more and more on in-chip Design for Test (DFT). The IC and SoC designer can add differentiation and value not just by incorporating design features and Design-for-Test for the IC, but by considering the target system that the IC/SoC may be used in. This practice is, of course, common in vertically integrated companies, but not standard practice by independent silicon vendors. The silicon vendor that can lower not only his customer’s cost of the part, but also the entire cost of using the silicon can gain a competitive advantage.