A fractional spur reduction technique for RF TDC-based all digital PLLs

In this paper, a technique is proposed to suppress the fractional spur induced by non-linearity of the loop in all digital PLLs (ADPLLs). The measurement results show that the fractional spurs are reduced by at least 9 dB, to below -75 dBc, when the technique is applied to a conventional all digital PLL (ADPLL) at 3.6 GHz. The extra silicon area needed for technique is only 0.02 mm2.

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