Design technique for simultaneous reduction of leakage power and contention current for wide fan-in domino logic based 32:1 multiplexer circuit

Domino circuits are becoming increasingly popular due to their speed and area advantages over their static counterparts. Every new generation of mobile processors employs domino circuits in critical paths to reduce delay. Multiplexers are one such combinational circuit finding extensive use in register files and execution units where data needs to be routed to one of the several operators. Power consumption, mainly due to contention and leakage currents poses problems of heat build up and performance degradation in domino circuits and this problem grows as the technology is scaled to subnanometer regimes. In this paper, a design technique has been proposed which reduces the contention and leakage currents simultaneously without much area overhead. The design has also been incorporated with a process variation sensor and simulations performed on the same to check for tolerance and the results have been found to conform to tolerance limits. The proposed technique uses only three extra transistors and minimizes contention current by about 74% and leakage by 38%, thus achieving a significant reduction in the average power consumption of the circuit.