An RHBD Technique to Mitigate Missing Pulses in Delay Locked Loops

A radiation-hardened-by-design (RHBD) voltage- controlled delay line (VCDL) for single-event mitigation in delay-locked loops (DLLs) is proposed. A modified fully differential delay cell topology is used to harden the VCDL, resulting in a dramatic reduction of the missing pulses generated by the DLL after an ion strike. By increasing the width-to-length ratios of the feedback transistors of the VCDL delay cells, this topology provides substantially reduced single-event errors while maintaining high operating frequency, wide tuning range and small area penalty.

[1]  C. Gendarme,et al.  CMOS Circuit Design, Layout, and Simulation, 2nd edition [Book Review] , 2006, IEEE Circuits and Devices Magazine.

[2]  T. D. Loveless,et al.  A Hardened-by-Design Technique for RF Digital Phase-Locked Loops , 2006, IEEE Transactions on Nuclear Science.

[3]  Shu-Ming Chang,et al.  A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[4]  A. Rofougaran,et al.  A 900 MHz CMOS LC-oscillator with quadrature outputs , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[5]  T. D. Loveless,et al.  A Probabilistic Analysis Technique Applied to a Radiation-Hardened-by-Design Voltage-Controlled Oscillator for Mixed-Signal Phase-Locked Loops , 2008, IEEE Transactions on Nuclear Science.

[6]  Jieh-Tsorng Wu,et al.  Phase averaging and interpolation using resistor strings or resistor rings for multi-phase clock generation , 2006, IEEE Trans. Circuits Syst. I Regul. Pap..

[7]  J.G. Maneatis,et al.  Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[8]  Sandeepan DasGupta,et al.  Trends in single event pulse widths and pulse shapes in deep submicron CMOS , 2007 .

[9]  M. Stojcev,et al.  Delay locked loop with linear delay element , 2005, TELSIKS 2005 - 2005 uth International Conference on Telecommunication in ModernSatellite, Cable and Broadcasting Services.

[10]  Yang-Han Lee,et al.  The CMOS on-chip oscillator based on level tracking technique , 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

[11]  T. D. Loveless,et al.  Modeling and Mitigating Single-Event Transients in Voltage-Controlled Oscillators , 2007, IEEE Transactions on Nuclear Science.