论文信息 - FROM TIMED AUTOMATA TO DEVS MODELS

FROM TIMED AUTOMATA TO DEVS MODELS

In this paper, we present the formal transformation of Timed Input/Output Automata into simulation models, expressed in the DEVS formalism. This transformation takes place in an approach of a validation of high-level specifications by simulation. The validation is based on the simulation of a coupled model built with the system to be controlled and the control specifications. An example of this approach is given in the paper.

D. J. Morrice | P. J. Sánchez | D. Ferrin

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