About robustness of test patterns regarding multiple faults
暂无分享,去创建一个
[1] Eduard Cerny,et al. Use of Fault Dropping for Multiple Fault Analysis , 1994, IEEE Trans. Computers.
[2] Hideo Fujiwara. Computational complexity of controllability/observability problems for combinational circuits , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.
[3] Bernd Becker,et al. ATPG-based grading of strong fault-secureness , 2009, 2009 15th IEEE International On-Line Testing Symposium.
[4] T. Sumioka,et al. Efficient techniques for multiple fault test generation , 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).
[5] Y. Takamatsu,et al. Test generation for combinational circuits with multiple faults , 1991, [1991] Proceedings Pacific Rim International Symposium on Fault Tolerant Systems.
[6] Irith Pomeranz,et al. On generating test sets that remain valid in the presence of undetected faults , 1997, Proceedings Great Lakes Symposium on VLSI.
[7] Melvin A. Breuer,et al. Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis , 1980, IEEE Transactions on Computers.
[8] El Mostapha Aboulhamid,et al. Multiple fault analysis using a fault dropping technique , 1991, [1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium.
[9] Alexander Saldanha,et al. Compact and complete test set generation for multiple stuck-faults , 1996, Proceedings of International Conference on Computer Aided Design.
[10] Paolo Prinetto,et al. Improved techniques for multiple stuck-at fault analysis using single stuck-at fault test sets , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.
[11] Sybille Hellebrand,et al. Verification and Analysis of Self-Checking Properties through ATPG , 2008, 2008 14th IEEE International On-Line Testing Symposium.
[12] Joseph L. A. Hughes. Multiple fault detection using single fault test sets , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[13] Ying Zhao,et al. A Multiple Faults Test Generation Algorithm Based on Neural Networks and Chaotic Searching for Digital Circuits , 2010, 2010 International Conference on Computational Intelligence and Software Engineering.
[14] Vishwani D. Agrawal,et al. Multiple fault detection in two-level multi-output circuits , 1992, J. Electron. Test..
[15] Raimund Ubar,et al. Structural fault collapsing by superposition of BDDs for test generation in digital circuits , 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).
[16] Eduard Cerny,et al. Test pattern generation for multiple stuck-at faults , 1993, Proceedings ETC 93 Third European Test Conference.
[17] James E. Smith. On Necessary and Sufficient Conditions for Multiple Fault Undetectability , 1979, IEEE Transactions on Computers.
[18] Eduard Cerny,et al. On the generation of test patterns for multiple faults , 1993, J. Electron. Test..
[19] John P. Hayes,et al. A Nand Model ror Fault Diagnosis in Combinational Logic Networks , 1971, IEEE Transactions on Computers.
[20] Vinod K. Agarwal,et al. Multiple Fault Testing of Large Circuits by Single Fault Test Sets , 1981, IEEE Transactions on Computers.
[21] Gernot Metze,et al. A New Representation for Faults in Combinational Digital Circuits , 1972, IEEE Transactions on Computers.
[22] Vishwani D. Agrawal,et al. Multiple faults: modeling, simulation and test , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.
[23] Se June Hong,et al. Cause-Effect Analysis for Multiple Fault Detection in Combinational Networks , 1971, IEEE Transactions on Computers.
[24] Janusz Rajski,et al. A method of fault analysis for test generation and fault diagnosis , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[25] Raimund Ubar,et al. Test Synthesis with Alternative Graphs , 1996, IEEE Des. Test Comput..
[26] W. Kent Fuchs,et al. MULTIPLE-FAULT SIMULATION AND COVERAGE OF DETERMINISTIC SINGLE-FAULT TEST SETS , 1991, 1991, Proceedings. International Test Conference.
[27] Raimund Ubar. Overview about Low-Level and High-Level Decision Diagrams for Diagnostic Modeling of Digital Systems Invited paper , 2011 .
[28] Kozo Kinoshita,et al. Test generation for multiple faults based on parallel vector pair analysis , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[29] Francisco J. O. Dias. Fault Masking in Combinational Logic Circuits , 1975, IEEE Transactions on Computers.
[30] A. Sangiovanni-Vincentelli,et al. Compact and complete test set generation for multiple stuck-faults , 1996, Proceedings of International Conference on Computer Aided Design.
[31] E. Macii,et al. Multiple stuck-at fault test generation techniques for combinational circuits based on network decomposition , 1993, Proceedings of 36th Midwest Symposium on Circuits and Systems.
[32] Zvi Kohavi,et al. Detection of Multiple Faults in Combinational Logic Networks , 1972, IEEE Transactions on Computers.