A 10-b 1-GHz 33-mW CMOS ADC

This paper describes a pipelined analog-to-digital converter that resolves 4 b in its first stage and amplifies the residue by a factor of 2, thereby relaxing the opamp linearity, voltage swing, and gain requirements. Calibration in the digital domain removes the effect of capacitor mismatches and corrects for the gain error. Using a one-stage opamp with a gain of 10 and realized in 65-nm CMOS technology, the ADC digitizes a 490-MHz input with a signal-to-(noise+distortion) ratio of 52.4 dB, achieving a figure of merit of 97 fJ/conversion-step.

[1]  A. Karanicolas,et al.  A 15-b 1-Msample/s digitally self-calibrated pipeline ADC , 1993 .

[2]  Greg Patterson,et al.  A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[3]  Behzad Razavi,et al.  A 10-bit 1-GHz 33-mW CMOS ADC , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[4]  L. Kushner,et al.  A process-scalable low-power charge-domain 13-bit pipeline ADC , 2008, 2008 IEEE Symposium on VLSI Circuits.

[5]  Seung-Chul Lee,et al.  A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[6]  I. Galton,et al.  A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC , 2004, IEEE Journal of Solid-State Circuits.

[7]  Behzad Razavi,et al.  A 12-Bit 200-MHz CMOS ADC , 2009, IEEE Journal of Solid-State Circuits.

[8]  Ian Galton,et al.  A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction , 2009, IEEE Journal of Solid-State Circuits.

[9]  Bang-Sup Song,et al.  Digital-domain calibration of multistep analog-to-digital converters , 1992 .

[10]  M. Vertregt,et al.  A 1.35 GS/s, 10b, 175 mW time-interleaved AD converter in 0.13 μm CMOS , 2007, 2007 IEEE Symposium on VLSI Circuits.

[11]  B. Razavi,et al.  A 10-Bit 500-MS/s 55-mW CMOS ADC , 2009, IEEE Journal of Solid-State Circuits.

[12]  Ying-Hsi Lin,et al.  An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[13]  Maarten Vertregt,et al.  A 1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[14]  Wenhua Yang,et al.  A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input , 2001, IEEE J. Solid State Circuits.

[15]  S. Devarajan,et al.  A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC , 2009, IEEE Journal of Solid-State Circuits.

[16]  F. A. Seiler,et al.  Numerical Recipes in C: The Art of Scientific Computing , 1989 .

[17]  D.A. Johns,et al.  An 11-Bit 45 MS/s Pipelined ADC With Rapid Calibration of DAC Errors in a Multibit Pipeline Stage , 2007, IEEE Journal of Solid-State Circuits.

[18]  Sanroku Tsukamoto,et al.  A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[19]  B. Murmann,et al.  A 12 b 75 MS/s pipelined ADC using open-loop residue amplification , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[20]  Jan Mulder,et al.  An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS , 2011, IEEE Journal of Solid-State Circuits.

[21]  Pier Andrea Francese,et al.  A 1.8 V 1.0 GS/s 10b Self-Calibrating Unified-Folding-Interpolating ADC With 9.1 ENOB at Nyquist Frequency , 2009, IEEE Journal of Solid-State Circuits.