Naxim: A Fast and Retargetable Network-on-Chip Simulator with QEMU and SystemC
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Hiroaki Takada | Ittetsu Taniguchi | Hiroyuki Tomiyama | Takuji Hieda | Keita Nakajima | Yusuke Fukutsuka | Shuto Kurebayashi
[1] Milo M. K. Martin,et al. Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset , 2005, CARN.
[2] Fabrice Bellard,et al. QEMU, a Fast and Portable Dynamic Translator , 2005, USENIX ATC, FREENIX Track.
[3] Atsushi Ike,et al. Fast cycle estimation methodology for instruction-level emulator , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[4] Jordi Carrabina,et al. Mixed SW/SystemC SoC Emulation Framework , 2007, 2007 IEEE International Symposium on Industrial Electronics.
[5] Axel Jantsch,et al. NNSE: Nostrum Network-on-Chip Simulation Environment , 2005 .
[6] Ming-Chao Chiang,et al. A QEMU and SystemC-Based Cycle-Accurate ISS for Performance Estimation on SoC Development , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[7] Somayeh Sardashti,et al. The gem5 simulator , 2011, CARN.
[8] Sameh A. Salem,et al. PPNOCS: Performance and Power Network on Chip Simulator based on SystemC , 2011 .
[9] Frédéric Pétrot,et al. On MPSoC Software Execution at the Transaction Level , 2011, IEEE Design & Test of Computers.
[10] Fredrik Larsson,et al. Simics: A Full System Simulation Platform , 2002, Computer.
[11] Frédéric Pétrot,et al. Using binary translation in event driven simulation for fast and flexible MPSoC simulation , 2009, CODES+ISSS '09.