Radix-based digital calibration techniques for multi-stage recycling pipelined ADCs
暂无分享,去创建一个
Dong-Young Chang | Un-Ku Moon | Jipeng Li | U. Moon | Jipeng Li | D. Chang
[1] T. W. Parks,et al. A Direct Code Error Calibration Technique for Two-step Flash A/D Converters , 1989 .
[2] Hae-Seung Lee,et al. A pipelined A/D conversion technique with near-inherent monotonicity , 1995 .
[3] Bang-Sup Song,et al. Interstage gain proration technique for digital-domain multi-step ADC calibration , 1994 .
[4] A. Karanicolas,et al. A 15-b 1-Msample/s digitally self-calibrated pipeline ADC , 1993 .
[5] Paul R. Gray,et al. A pipelined 13-bit 250-ks/s 5-V analog-to-digital converter , 1988 .
[6] Hae-Seung Lee. A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC , 1994 .
[7] Stephen H. Lewis,et al. A 10-b 20-Msample/s analog-to-digital converter , 1992 .
[8] Un-Ku Moon,et al. A 0.9 V 9 mW 1MSPS digitally calibrated ADC with 75 dB SFDR , 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).
[9] Paul R. Gray,et al. A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mu m CMOS , 1991 .
[10] S.-H. Lee,et al. A direct code error calibration technique for two-step flash A/D converters , 1989 .
[11] H. Onodera,et al. A cyclic A/D converter that does not require ratio-matched components , 1987, 1987 Symposium on VLSI Circuits.
[12] Bruce A. Wooley,et al. A continuously calibrated 12-b, 10-MS/s, 3.3-V A/D converter , 1998 .
[13] Bang-Sup Song,et al. A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter , 1988 .
[14] D.A. Hodges,et al. A self-calibrating 15 bit CMOS A/D converter , 1984, IEEE Journal of Solid-State Circuits.
[15] P. R. Gray,et al. Reference refreshing cyclic analog-to-digital and digital-to-analog converters , 1986 .
[16] R. Castello,et al. A ratio-independent algorithmic analog-to-digital conversion technique , 1984, IEEE Journal of Solid-State Circuits.
[17] Dong-Young Chang,et al. Radix-based digital calibration technique for multi-stage ADC , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).
[18] John W. Fattaruso,et al. Error correction techniques for high-performance differential A/D converters , 1990 .
[19] Yun Chiu,et al. Inherently linear capacitor error-averaging techniques for pipelined A/D conversion , 2000 .
[20] Bang-Sup Song,et al. A 15 b 5 MSample/s low-spurious CMOS ADC , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.
[21] Paul R. Gray,et al. A CMOS programmable self-calibrating 13-bit eight-channel data acquisition peripheral , 1987 .
[22] P.J. Hurst,et al. A 12 b digital-background-calibrated algorithmic ADC with -90 dB THD , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).
[23] Un-Ku Moon,et al. Background digital calibration techniques for pipelined ADCs , 1997 .