Parametric Yield Analysis and Optimization in Leakage Dominated Technologies

Parametric yield loss has become a serious concern in nanometer technologies. In this paper, we propose a methodology to estimate and optimize the parametric yield of a design in the presence of process variations. We discuss the impact of leakage on parametric yield given that leakage causes the parametric yield window to shrink by imposing a two-sided constraint in conjunction with performance targets on the yield window. We present a mathematical framework for yield estimation under process variation for a given power and frequency constraints. The model is validated against Monte Carlo SPICE simulations in a 90-nm CMOS process and is shown to have a typical error of less than 5%. We then demonstrate the importance of optimal supply and threshold voltage selection for yield maximization. Our results show that parametric yield is highly sensitive to supply voltage with only a 5% change in the supply voltage potentially leading to nearly 15% yield degradation. We also investigate the sensitivity of parametric yield to required frequency and power constraints. Finally, we apply the proposed framework to the problem of maximizing the shipping frequency in the presence of given yield and power constraints.

[1]  Sachin S. Sapatnekar,et al.  Full-chip analysis of leakage power under process variations, including spatial correlations , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[2]  R. Keyes.  The effect of randomness in the distribution of impurity atoms on FET thresholds , 1975 .

[3]  David Blaauw,et al.  Statistical analysis of subthreshold leakage current for VLSI circuits , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  David Blaauw,et al.  Statistical timing analysis using bounds and selective enumeration , 2003, TAU '02.

[5]  Natesan Venkateswaran,et al.  First-Order Incremental Block-Based Statistical Timing Analysis , 2006, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Kiyoyuki Terakura,et al.  KINETICS OF INITIAL LAYER-BY-LAYER OXIDATION OF SI(001) SURFACES , 1998 .

[7]  James Tschanz,et al.  Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[8]  Christer Svensson,et al.  Trading speed for low power by choice of supply and threshold voltages , 1993 .

[9]  E. Nowak,et al.  High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res And Dev , 2006 .

[10]  M.J.M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[11]  David Blaauw,et al.  Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[12]  Subhasish Mitra,et al.  Delay defect characteristics and testing strategies , 2003, IEEE Design & Test of Computers.

[13]  Sani R. Nassif,et al.  Modeling and analysis of manufacturing variations , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[14]  Michael Orshansky,et al.  Fast statistical timing analysis handling arbitrary delay correlations , 2004, Proceedings. 41st Design Automation Conference, 2004..

[15]  Vivek De,et al.  Technology and design challenges for low power and high performance [microprocessors] , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[16]  B. M. Gordon,et al.  Supply and threshold voltage scaling for low power CMOS , 1997, IEEE J. Solid State Circuits.

[17]  Yuan Taur,et al.  Fundamentals of Modern VLSI Devices , 1998 .

[18]  Rohit Kapur,et al.  Speed binning with path delay test in 150-nm technology , 2003, IEEE Design & Test of Computers.

[19]  T. Ono,et al.  Limit of gate oxide thickness scaling in MOSFETs due to apparent threshold voltage fluctuation induced by tunnel leakage current , 2001 .

[20]  James D. Meindl,et al.  Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration , 2002, IEEE J. Solid State Circuits.

[21]  Kurt Keutzer,et al.  From blind certainty to informed uncertainty , 2002, TAU '02.

[22]  Puneet Gupta,et al.  Design sensitivities to variability: extrapolations and assessments in nanometer VLSI , 2002, 15th Annual IEEE International ASIC/SOC Conference.

[23]  S. Narasimha,et al.  A high performance 90nm SOI technology with 0.992 /spl mu/m2 6T-SRAM cell , 2002, Digest. International Electron Devices Meeting,.

[24]  A. Toriumi,et al.  Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET's , 1994 .

[25]  Sachin S. Sapatnekar,et al.  Statistical timing analysis considering spatial correlations using a single PERT-like traversal , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[26]  Vivek De,et al.  Technology and design challenges for low power and high performance [microprocessors] , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[27]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について － , 2004 .

[28]  S. Nassif,et al.  Delay variability: sources, impacts and trends , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[29]  A. R. Newton,et al.  Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .

[30]  Ulrich Ramacher,et al.  A 100-GOPS programmable processor for vehicle vision systems , 2003, IEEE Design & Test of Computers.

[31]  David Blaauw,et al.  Parametric yield estimation considering leakage variability , 2004, Proceedings. 41st Design Automation Conference, 2004..