Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

In this work, experimental assessment of the variability of threshold voltage and drain current in junctionless nanowire $n$ MOS transistors is presented. Die-to-die variability of threshold voltage and drain current is presented and compared to inversion mode nanowire with the same dimensions. Although the junctionless nanowires have shown larger threshold voltage matching coefficients than inversion mode devices, the variability obtained experimentally has shown to be smaller than predicted by some simulations reported in the literature. Also, it has been shown that as the channel length of junctionless nanowire transistors is reduced, the current variability becomes smaller than in inversion mode nanowires, at the same current level and dimensions.

[1]  C. O. Chui,et al.  Variability Impact of Random Dopant Fluctuation on Nanoscale Junctionless FinFETs , 2012, IEEE Electron Device Letters.

[2]  Ran Yan,et al.  Junctionless Multiple-Gate Transistors for Analog Applications , 2011, IEEE Transactions on Electron Devices.

[3]  T. Serrano-Gotarredona,et al.  MOSFET mismatch in weak/moderate inversion: model needs and implications for analog design , 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

[4]  B. McCarthy,et al.  SOI gated resistor: CMOS without junctions , 2009, 2009 IEEE International SOI Conference.

[5]  Chi-Woo Lee,et al.  Nanowire transistors without junctions. , 2010, Nature nanotechnology.

[6]  Antonio J. García-Loureiro,et al.  FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability , 2018, IEEE Journal of the Electron Devices Society.

[7]  Marcel J. M. Pelgrom,et al.  Matching properties of MOS transistors , 1988, ESSCIRC '88: Fourteenth European Solid-State Circuits Conference.

[8]  G. Ghibaudo,et al.  Drain current local variability analysis in nanoscale junctionless FinFETs utilizing a compact model , 2020 .

[9]  Juin J. Liou,et al.  Revisiting MOSFET threshold voltage extraction methods , 2013, Microelectron. Reliab..

[10]  A. Lucibello,et al.  Variability of the Drain Current in Junctionless Nanotransistors Induced by Random Dopant Fluctuation , 2014, IEEE Transactions on Electron Devices.

[11]  R. Trevisoli,et al.  Effective channel length in Junctionless Nanowire Transistors , 2015, 2015 30th Symposium on Microelectronics Technology and Devices (SBMicro).

[12]  Wim Magnus,et al.  Analytical and self-consistent quantum mechanical model for a surrounding gate MOS nanowire operated in JFET mode , 2008 .

[13]  T. Numata,et al.  Unified understanding of Vth and Id variability in tri-gate nanowire MOSFETs , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

[14]  N. Horiguchi,et al.  Variability sources in nanoscale bulk FinFETs and TiTaN- a promising low variability WFM for 7/5nm CMOS nodes , 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

[15]  A. Gnudi,et al.  Analysis of Threshold Voltage Variability Due to Random Dopant Fluctuations in Junctionless FETs , 2012, IEEE Electron Device Letters.

[16]  X. Garros,et al.  All-operation-regime characterization and modeling of drain current variability in junctionless and inversion-mode FDSOI transistors , 2020, 2020 IEEE Symposium on VLSI Technology.