Macro-cell placement for analog physical designs using a hybrid genetic algorithm with simulated annealing

Practical analog layout synthesis techniques have been the subject of active research for the past two decades to address the growing gap between the increasing chip functionality and the design productivity. In this paper, we present a novel macro-cell placement approach following the optimization flow of a genetic algorithm controlled by the methodology of simulated annealing. A process of cell slide is adopted to drastically reduce the configuration space without degrading search opportunities. In addition, this cell-slide process is used to satisfy the symmetry constraints essential for analog layouts. Furthermore, the dedicated cost function captures subtle electrical and geometrical constraints, such as area, net length, aspect ratio, proximity, parasitic effects, etc. required for analog layout and subsequent intellectual property reuse. To study the algorithm parameters, fractional factorial experiments and a meta-GA approach are employed. The proposed algorithm has been tested using several analog circuits. Compared to the simulated-annealing approach, the dominant one currently used for the analog placement problem, the proposed algorithm requires less computation time while generating higher quality layouts, comparable to expert manual placements. Furthermore, our hybrid algorithm and the method of parameter optimization can be readily adapted to different optimization problems across disciplines.

[1]  Georges Gielen,et al.  Analog layout generation for performance and manufacturability , 1999 .

[2]  Lihong Zhang,et al.  A genetic approach to analog module placement with simulated annealing , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[3]  B. Martin.  Automation comes to analog , 2001 .

[4]  Rob A. Rutenbar,et al.  Computer-aided design of analog and mixed-signal integrated circuits , 2000, Proceedings of the IEEE.

[5]  K. Handa,et al.  Polycell placement for analog LSI chip designs by genetic algorithms and tabu search , 1995, Proceedings of 1995 IEEE International Conference on Evolutionary Computation.

[6]  A. Sangiovanni-Vincentelli,et al.  The TimberWolf placement and routing package , 1985, IEEE Journal of Solid-State Circuits.

[7]  C. L. Liu,et al.  A New Algorithm for Floorplan Design , 1986, DAC 1986.

[8]  S. W. Mehranfar.  A technology-independent approach to custom analog cell generation , 1991 .

[9]  John M. Cohn.  Analog Device-Level Layout Automation , 1994 .

[10]  Suat Tanaydin.  Robust Design and Analysis for Quality Engineering , 1996 .

[11]  H. W. Li,et al.  Analog layout using ALAS , 1996 .

[12]  Rob A. Rutenbar,et al.  Layout tools for analog ICs and mixed-signal SoCs: a survey , 2000, ISPD '00.

[13]  Majid Sarrafzadeh,et al.  Dragon2000: standard-cell placement tool for large industry circuits , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[14]  Pinaki Mazumder,et al.  Macro-cell and module placement by genetic adaptive search with bitmap-represented chromosome , 1991, Integr..

[15]  Oliver Vornberger,et al.  Hybrid genetic algorithms for constrained placement problems , 1997, IEEE Trans. Evol. Comput..

[16]  Sadiq M. Sait,et al.  VLSI Physical Design Automation - Theory and Practice , 1995, Lecture Notes Series on Computing.

[17]  J. Litsios,et al.  ILAC: an automated layout tool for analog CMOS circuits , 1989 .

[18]  Bah-Hwee Gwee,et al.  A GA with heuristic-based decoder for IC floorplanning , 1999, Integr..

[19]  Oliver Vornberger,et al.  Genetic packing of rectangles on transputers , 1991 .

[20]  Frank M. Johannes,et al.  Generic global placement and floorplanning , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[21]  Massoud Pedram,et al.  Timing-driven placement based on partitioning with dynamic cut-net control , 2000, DAC.

[22]  Bedrich J. Hosticka,et al.  A novel analog module generator environment , 1996, Proceedings ED&TC European Design and Test Conference.

[23]  Igor L. Markov,et al.  Quadratic placement revisited , 1997, DAC.

[24]  Lester Ingber,et al.  Simulated annealing: Practice versus theory , 1993 .

[25]  Franco Maloberti,et al.  Analog Design for CMOS VLSI Systems , 2001 .

[26]  U. Kleine,et al.  A novel class of complementary folded-cascode opamps for low voltage , 2002 .

[27]  Elizabeth M. Rudnick,et al.  Genetic algorithms for VLSI design, layout & test automation , 1999 .

[28]  Lihong Zhang,et al.  A new design rule description for automated layout tools , 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

[29]  Georges Gielen,et al.  A performance-driven placement tool for analog integrated circuits , 1995 .

[30]  U. Kleine,et al.  A Common Mode Feedback Structure for Differential OpAmps Using NMOS Depletion Transistors , 2001 .

[31]  Pinaki Mazumder,et al.  SAGA : a unification of the genetic algorithm with simulated annealing and its application to macro-cell placement , 1994, Proceedings of 7th International Conference on VLSI Design.

[32]  田口 玄一,et al.  Taguchi methods, research and development , 1992 .

[33]  Pinaki Mazumder,et al.  A genetic approach to standard cell placement using meta-genetic parameter optimization , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..