Toward the tools selection in model based system engineering for embedded systems - A systematic literature review
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[1] Eugenio Villar,et al. Generating heterogeneous executable specifications in SystemC from UML/MARTE models , 2010, Innovations in Systems and Software Engineering.
[2] Lisane B. de Brisolara,et al. Integrating UML, MARTE and sysml to improve requirements specification and traceability in the embedded domain , 2014, 2014 12th IEEE International Conference on Industrial Informatics (INDIN).
[3] Elvinia Riccobene,et al. Integrating the SysML and the SystemC-UML profiles in a model-driven embedded system design flow , 2012, Design Automation for Embedded Systems.
[4] Marco A. Wehrmeister,et al. Automatic code generation for embedded systems: From UML specifications to VHDL code , 2010, 2010 8th IEEE International Conference on Industrial Informatics.
[5] Samir Chouali,et al. Formal verification of components assembly based on SysML and interface automata , 2011, Innovations in Systems and Software Engineering.
[6] Lionel C. Briand,et al. Environment modeling and simulation for automated testing of soft real-time embedded software , 2013, Software & Systems Modeling.
[7] Payman Behnam,et al. Formal equivalence verification and debugging techniques with auto-correction mechanism for RTL designs , 2013, Microprocess. Microsystems.
[8] Masahiro Fujita,et al. On the integration of model-driven design and dynamic assertion-based verification for embedded software , 2013, J. Syst. Softw..
[9] Lei Feng,et al. An architectural approach to the analysis, verification and validation of software intensive embedded systems , 2013, Computing.
[10] Da He,et al. The SATURN Approach to SysML-Based HW/SW Codesign , 2010, ISVLSI.
[11] Marta Z. Kwiatkowska,et al. PRISM 4.0: Verification of Probabilistic Real-Time Systems , 2011, CAV.
[12] Juan de Lara,et al. Towards the flexible reuse of model transformations: A formal approach based on graph transformation , 2014, J. Log. Algebraic Methods Program..
[13] Marco A. Wehrmeister,et al. GenERTiCA: A Tool for Code Generation and Aspects Weaving , 2008, 2008 11th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC).
[14] Jung-Soo Han,et al. Model transformation verification using similarity and graph comparison algorithm , 2013, Multimedia Tools and Applications.
[15] Mara Nikolaidou,et al. Model-based system engineering using SysML: Deriving executable simulation models with QVT , 2014, 2014 IEEE International Systems Conference Proceedings.
[16] T. Sakairi,et al. Designing a control system using SysML and Simulink , 2012, 2012 Proceedings of SICE Annual Conference (SICE).
[17] Adrian Rutle,et al. A formal approach to the specification and transformation of constraints in MDE , 2012, J. Log. Algebraic Methods Program..
[18] Leandro Soares Indrusiak,et al. MADES FP7 EU project: Effective high level SysML/MARTE methodology for real-time and embedded avionics systems , 2012, 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC).
[19] Marian Adamski,et al. Translation UML diagrams into Verilog , 2014, 2014 7th International Conference on Human System Interactions (HSI).
[20] Robert de Simone,et al. Safe CCSL specifications and marked graphs , 2013, 2013 Eleventh ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2013).
[21] Rached Tourki,et al. System level modeling methodology of NoC design from UML-MARTE to VHDL , 2012, Des. Autom. Embed. Syst..
[22] Péter Fehér,et al. The challenges of a model transformation language , 2012, 2012 IEEE 19th International Conference and Workshops on Engineering of Computer-Based Systems.
[23] Pierre Boulet,et al. Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: Advantages, limitations and alternatives , 2012, J. Syst. Archit..
[24] Zuohua Ding,et al. Schedulability Analysis with CCSL Specifications , 2013, 2013 20th Asia-Pacific Software Engineering Conference (APSEC).
[25] MarcosEsperanza,et al. Applying MDE to the (semi-)automatic development of model transformations , 2013 .
[26] Esperanza Marcos,et al. Applying MDE to the (semi-)automatic development of model transformations , 2013, Inf. Softw. Technol..
[27] S. H. M. Durand,et al. A tool to support Bluespec SystemVerilog coding based on UML diagrams , 2012, IECON 2012 - 38th Annual Conference on IEEE Industrial Electronics Society.
[28] Siobhán Clarke,et al. An aspect-oriented, model-driven approach to functional hardware verification , 2012, J. Syst. Archit..
[29] Eduard Paul Enoiu,et al. A SysML model for code correction and detection systems , 2010, The 33rd International Convention MIPRO.
[30] Christophe Moy,et al. A co-design methodology based on model driven architecture for real time embedded systems , 2011, Math. Comput. Model..
[31] Mara Nikolaidou,et al. Integrating simulation capabilities into SysML for enterprise information system design , 2014, 2014 9th International Conference on System of Systems Engineering (SOSE).
[32] Frank Budinsky,et al. Eclipse Modeling Framework , 2003 .
[33] Erwan Bousse,et al. Aligning SysML with the B method to provide V&V for systems engineering , 2012, MoDeVVa '12.
[34] Marian Adamski,et al. UML state machine implementation in FPGA devices by means of dual model and Verilog , 2013, 2013 11th IEEE International Conference on Industrial Informatics (INDIN).
[35] Paulo Cézar Stadzisz,et al. A Brazilian survey on UML and model-driven practices for embedded software development , 2013, J. Syst. Softw..
[36] Franklin Ramalho,et al. MetaTT - A Metamodel Based Approach for Writing Textual Transformations , 2012, 2012 Sixth Brazilian Symposium on Software Components, Architectures and Reuse.
[37] Deyuan Gao,et al. Formal verification of mixed-signal circuits using extended PSL , 2009, 2009 IEEE 8th International Conference on ASIC.
[38] Doo-Hwan Bae,et al. Automatic construction of timing diagrams from UML/MARTE models for real-time embedded software , 2014, SAC.
[39] Jun Chen,et al. Engineering of An Assertion-based PSLSimple-Verilog Dynamic Verifier by Alternating Automata , 2008, Electron. Notes Theor. Comput. Sci..
[40] W. Gareth J. Howells,et al. A Model-Driven Development Approach to Mapping UML State Diagrams to Synthesizable VHDL , 2008, IEEE Transactions on Computers.
[41] Barbara Kitchenham,et al. Procedures for Performing Systematic Reviews , 2004 .
[42] Wim Dehaene,et al. UML for electronic systems design: a comprehensive overview , 2008, Des. Autom. Embed. Syst..
[43] Roy Grønmo,et al. Comparison of Three Model Transformation Languages , 2009, ECMDA-FA.
[44] Richard F. Paige,et al. A feature model for model-to-text transformation languages , 2012, 2012 4th International Workshop on Modeling in Software Engineering (MISE).
[45] Luciano Baresi,et al. Formal verification and validation of embedded systems: the UML-based MADES approach , 2015, Software & Systems Modeling.
[46] Dionísio Doering. A model driven engineering methodology for embedded system designs — HIPAO2 , 2014, 2014 12th IEEE International Conference on Industrial Informatics (INDIN).
[47] Julien DeAntoni,et al. Multi-view Power Modeling Based on UML, MARTE and SysML , 2012, 2012 38th Euromicro Conference on Software Engineering and Advanced Applications.
[48] Bahram N. Uchevler,et al. Assertion based verification using PSL-like properties in Haskell , 2013, 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).
[49] Gustavo Rau de Almeida Callou,et al. A Methodology for Mapping SysML Activity Diagram to Time Petri Net for Requirement Validation of Embedded Real-Time Systems with Energy Constraints , 2009, 2009 Third International Conference on Digital Society.
[50] Frédéric Mallet. Automatic generation of observers from MARTE/CCSL , 2012, 2012 23rd IEEE International Symposium on Rapid System Prototyping (RSP).
[51] Juan de Lara,et al. A Visual Specification Language for Model-to-Model Transformations , 2010, 2010 IEEE Symposium on Visual Languages and Human-Centric Computing.
[52] Bran Selic,et al. Extending SysML with AADL Concepts for Comprehensive System Architecture Modeling , 2011, ECMFA.
[53] Samir Ouchani,et al. A formal verification framework for Bluespec System Verilog , 2013, Proceedings of the 2013 Forum on specification and Design Languages (FDL).
[54] Ekkart Kindler,et al. Comparing relational model transformation technologies: implementing Query/View/Transformation with Triple Graph Grammars , 2009, Software & Systems Modeling.
[55] A. Hammad,et al. Transformation of SysML Structure Diagrams to VHDL-AMS , 2012, 2012 Second Workshop on Design, Control and Software Implementation for Distributed MEMS.
[56] Keijo Heljanko,et al. Efficient Model Checking of PSL Safety Properties , 2010, 2010 10th International Conference on Application of Concurrency to System Design.
[57] Ahmed Hammad,et al. Mapping SysML to modelica to validate wireless sensor networks non-functional requirements , 2013, 2013 11th International Symposium on Programming and Systems (ISPS).
[58] Pieter Van Gorp,et al. Evaluation of model transformation approaches for model refactoring , 2014, Sci. Comput. Program..
[59] Guy Gogniat,et al. A co-design approach for embedded system modeling and code generation with UML and MARTE , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.
[60] Bran Selic,et al. Challenges in Combining SysML and MARTE for Model-Based Design of Embedded Systems , 2009, ECMDA-FA.
[61] Xavier Crégut,et al. Formal Specification and Verification of Task Time Constraints for Real-Time Systems , 2012, ISoLA.
[62] Ludovic Apvrille,et al. TEPE: a SysML language for time-constrained property modeling and formal verification , 2011, SOEN.
[63] Samir Ouchani,et al. A formal verification framework for SysML activity diagrams , 2014, Expert Syst. Appl..
[64] Gianmaria De Tommasi,et al. Modeling of MARTe-Based Real-Time Applications With SysML , 2013, IEEE Transactions on Industrial Informatics.
[65] Minxue Pan,et al. An MDE-based approach to the verification of SysML state machine diagram , 2012, Internetware.
[66] Gianluca Palermo,et al. The COMPLEX methodology for UML/MARTE Modeling and design space exploration of embedded systems , 2014, J. Syst. Archit..