Sub-sampling predictive line search algorithm for multimedia processors

Most of fast block motion estimation algorithms reported so far in literatures aim to reduce the computation in terms of the number of search points, thus do not fit well with multimedia processors due to their irregular data flow. For multimedia processors, proper reuse of data is more important than reducing number of absolute difference operations because the execution cycle performance strongly depends on the number of off-chip memory access. Therefore, in this paper, we propose a sub-sampling predictive line search (SS-PLS) algorithm using line search pattern which can increase data reuse from on-chip local buffer, and check sub-sampling points in line search pattern to reduce unnecessary SAD operation. Our experimental results show that the prediction error (MAE) performance of the proposed SS-PLS is similar to that of the full search block matching algorithm (FSBMA), while compared with the hexagonal-based search (HEXBS), the SS-PLS outperforms. Also the proposed SS-PLS requires much lower off-chip memory access than the conventional fast motion estimation algorithm such as the hexagonal-based search (HEXBS) and the predictive line search (PLS). As a result, the proposed SS-PLS algorithm requires lower number of execution cycles in multimedia processor.