Reusing Leakage Current for Improved Energy Efficiency of Multi-Voltage Systems

A novel method for the delivery of power to subthreshold (sub-Vt) circuits is proposed. The unused leakage current during idle-mode operation of super-threshold (super-Vt) circuits is used to supply sub-Vt circuits. Super-Vt and sub-Vt circuits are simulated in a 45 nm CMOS technology, where the super-Vt circuits operate at 1.2 V and generate a sub-Vt voltage of 380 mV. The proposed technique is compared with two conventional methods, one that uses separate power distribution networks for super-Vt and sub-Vt circuits (baseline) and the second that implements voltage stacking. The implementation of the proposed leakage reuse (LR) technique on the s27 ISCAS89 benchmark circuit results in a reduction of the total, static, and peak power consumption to, respectively, 0.41×, 0.207×, and 0.7× that of the baseline technique. The leakage reuse technique also reduces the peak voltage noise on VSS and the VSS settling time to, respectively, 0.68× and 0.44× that of the baseline at a cost of a 1.24× increase in the FO4 delay. In addition, the LR technique implemented on the s208 ISCAS89 benchmark circuit reduces the peak voltage noise on the virtual ground (VGND) and the VGND settling time to, respectively, 0.28× and 0.23× that of the voltage stacking technique.

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