Low-power radix-8 divider
暂无分享,去创建一个
[1] Mark Horowitz,et al. SRT division architectures and implementations , 1997, Proceedings 13th IEEE Sympsoium on Computer Arithmetic.
[2] M. Ercegovac,et al. Division and Square Root: Digit-Recurrence Algorithms and Implementations , 1994 .
[3] Massoud Pedram,et al. Low power design methodologies , 1996 .
[4] Tomás Lang,et al. Low-power radix-4 divider , 1996, ISLPED '96.
[5] Gregory B. Zyner,et al. 167 MHz radix-8 divide and square root using overlapped radix-2 stages , 1995, Proceedings of the 12th Symposium on Computer Arithmetic.
[6] Anantha P. Chandrakasan,et al. Low Power Digital CMOS Design , 1995 .
[7] Alberto Nannarelli. PET: Power Evaluation Tool , 1996 .
[8] Jan Fandrianto. Algorithm for high speed shared radix 8 division and radix 8 square root , 1989, Proceedings of 9th Symposium on Computer Arithmetic.
[9] José C. Monteiro,et al. Retiming sequential circuits for low power , 1993, ICCAD.
[10] Srinivas Devadas,et al. Retiming sequential circuits for low power , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[11] Mark Horowitz,et al. Clustered voltage scaling technique for low-power design , 1995, ISLPED '95.