SVA checker generator for FPGA-based verification platform

This paper discusses development of FPGA-based verification platform which consists of System' Verilog assertion (SVA) checker generator to synthesize SVA into Verilog code. We derive a lookup table that consists of SVA operators and their corresponding synthesizable RTL coding. Assertion checker produces single bit-1 which indicates an assertion fails while assertion collection modules must be simple and fast enough to collect the assertion results from assertion checker. In our work, collection module is implemented as arbiter and memory blocks. Case studies have been conducted on 8-bit counter and 8-bit FIFO with 10 assertions and 8 design bugs. Comparison has been done with assertion checker derived from MBAC approach in terms of checker's size. The comparison has showed that the checker size can be reduced further for 17.39%.

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