Random test generation using concurrent logic simulation

All approaches to automatic test generation consist of two complementary parts, namely, the generation of test vectors and verification to measure their adequacy. Path sensitizing is a well-known basic approach in which highly complex techniques used for vector generation represent the major effort in the generation/verification process. The second basic approach, random generation of vectors, is simpler but requires very efficient verification techniques if the program is to work well. Here we are concerned with the application of new verification methods to the random generation approach. Random test generation (RTG) procedures have been used previously (1,2,3) but they have not been well received by CAD practitioners compared to the newer non-random path sensitizing procedures. (4,5,6) Then why return to RTG? Based on our belief that the best test generation system should be a combination of RTG and path sensitizing techniques, it was decided to start with the easier method to implement. Equally important, however, was the development of new verification methods (7,9) which make a random approach seem much more attractive.