Machine learning-based dynamic reconfiguration algorithm for reconfigurable NoCs

Hybrid optical-electro Network-on-Chip (HOE_NoC) is a disruptive technology that can provide high bandwidth and low latency for global communication. However, optical links suffers with a problem of large static power consumption in network. For different applications, traffic distribution in space and time may differ largely. Therefore, it is necessary to dynamically provide optical link bandwidth to network for higher power efficiency under all traffic distribution. In this paper, we propose a machine learning-based dynamic reconfiguration algorithm for reconfigurable NoCs (RHOE_NoC) to reduce the static power. With machine learning prediction technique, we reconfigure the optical nodes dynamically to adapt different traffic demands while maintaining higher performance. Experimental results shown that as compared to electronic network latency has been reduced by 51%, while throughput has been improved by 14% for 64 node network architecture and energy consumption has been reduced by 26%. We have also compared RHOE_NoC with HOE_NoC without reconfiguration, results show that static energy consumption has been reduced by about 28%.

[1]  Alyssa B. Apsel,et al.  Analysis of challenges for on-chip optical interconnects , 2009, GLSVLSI '09.

[2]  Natalie D. Enright Jerger,et al.  QuT: A low-power optical Network-on-Chip , 2014, 2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

[3]  Ning Wu,et al.  A Novel Non-cluster Based Architecture of Hybrid Electro-optical Network-on-Chip , 2022 .

[4]  Chen Sun,et al.  DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

[5]  Haoran Li,et al.  JADE: a Heterogeneous Multiprocessor System Simulation Platform Using Recorded and Statistical Application Models , 2016, AISTECS '16.

[6]  William J. Dally,et al.  Research Challenges for On-Chip Interconnection Networks , 2007, IEEE Micro.

[7]  Ahmed Louri,et al.  Three-Dimensional Stacked Nanophotonic Network-on-Chip Architecture with Minimal Reconfiguration , 2014, IEEE Transactions on Computers.

[8]  Jung Ho Ahn,et al.  Corona: System Implications of Emerging Nanophotonic Technology , 2008, 2008 International Symposium on Computer Architecture.

[9]  Christopher Batten,et al.  Silicon-photonic clos networks for global on-chip communication , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[10]  Wei Zhang,et al.  A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip , 2012, JETC.

[11]  Hannu Tenhunen,et al.  Optimal placement of vertical connections in 3D Network-on-Chip , 2013, J. Syst. Archit..

[12]  Li Zhou,et al.  PROBE: Prediction-based optical bandwidth scaling for energy-efficient NoCs , 2013, 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS).