Understanding transient latchup hazards and the impact of guard rings

An experimental study of transient latchup is conducted. Measurements are performed on test structures fabricated in 90-nm and 130-nm CMOS technologies. The worst case testing conditions differ for static and transient latchup. Device simulation is used to understand the measurement results. P-well and N-well guard rings are evaluated under transient test conditions.

[1]  Ronald R. Troutman.  Latchup in CMOS Technology , 1986 .

[2]  W. Stadler,et al.  Development strategy for TLU-robust products , 2004, 2004 Electrical Overstress/Electrostatic Discharge Symposium.

[3]  W. Morris,et al.  Latchup in CMOS , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[4]  E. Rosenbaum,et al.  Guard Ring Interactions and their Effect on CMOS Latchup Resilience , 2008, 2008 IEEE International Electron Devices Meeting.

[5]  E. Rosenbaum,et al.  Transmission line pulsed waveform shaping with microwave filters , 2003, 2003 Electrical Overstress/Electrostatic Discharge Symposium.

[6]  E. Rosenbaum,et al.  Analytical modeling of external latchup , 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

[7]  K. Chatty,et al.  External Latchup Characteristics Under Static and Transient Conditions in Advanced Bulk CMOS Technologies , 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

[8]  E. Rosenbaum,et al.  Modeling of majority and minority carrier triggered external latchup , 2008, 2008 IEEE International Reliability Physics Symposium.

[9]  K. Chatty,et al.  Investigation of External Latchup Robustness of Dual and Triple Well Designs in 65nm Bulk CMOS Technology , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[10]  Ronald R. Troutman,et al.  Latchup in CMOS Technology: The Problem and Its Cure , 1986 .