Verifying Temporal Properties of Sequential Machines without Building Their State Diagrams

This paper presents the algorithm we have developed for proving that a finite state machine holds some properties expressed in temporal logic. This algorithm does not require the building of the state-transition graph nor the transition relation of the machine, so it overcomes the limits of the methods that have been proposed in the past. The verification algorithm presented here is based on Boolean function manipulations, which are represented by typed decision graphs. Thanks to this canonical representation, all the operations used in the algorithm have a polynomial complexity, expect for one called the computation of the “critical term”. The paper proposes techniques that reduce the computational cost of this operation.