Geometric Model Checking: An Automatic Verification Technique for Loop and Data Reuse Transformations

Optimizing programs by applying source-to-source transformations is a prevalent practice among programmers. Particularly so, in the framework of methodology based embedded systems design, where the initial program is subject to a series of transformations to optimize computation and communication. In the context of parallelization and custom memory design, such transformations are applied on the loop structures and index expressions of array variables in the program, more often manually than with a tool, leading to the non-trivial problem of checking their correctness. Applied transformations are semantics preserving if the transformed program is functionally equivalent to the initial program from the input-output point of view. In this work we present an automatic technique based on geometrical program modeling to formally check the functional equivalence of initial and transformed programs under loop and data reuse transformations. Our technique also provides very useful diagnostics to locate the detected errors.

[1]  William Pugh,et al.  A practical algorithm for exact array dependence analysis , 1992, CACM.

[2]  Francky Catthoor,et al.  Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design , 1998 .

[3]  H. De Man,et al.  SynGuide: An environment for doing interactive correctness preserving transformations , 1993, Proceedings of IEEE Workshop on VLSI Signal Processing.

[4]  Monica S. Lam,et al.  A Loop Transformation Theory and an Algorithm to Maximize Parallelism , 1991, IEEE Trans. Parallel Distributed Syst..

[5]  William Pugh,et al.  The Omega test: A fast and practical integer programming algorithm for dependence analysis , 1991, Proceedings of the 1991 ACM/IEEE Conference on Supercomputing (Supercomputing '91).

[6]  Srinivas Devadas,et al.  Event-based verification of synchronous, globally controlled, logic designs against signal flow graphs , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Sanjay V. Rajopadhye,et al.  Optimizing memory usage in the polyhedral model , 2000, TOPL.

[8]  Utpal Banerjee Loop Parallelization , 1994, Springer US.

[9]  Gerhard Goos,et al.  Issues in Compiling , 2001, J. Univers. Comput. Sci..

[10]  Lothar Thiele,et al.  ON THE SYNTHESIS OF MASSIVELY PARALLEL ARCHITECTURES , 1993 .

[11]  Hugo De Man,et al.  Efficient functional validation of system-level loop transformations for multi-media applications , 1997 .

[12]  Axel Jantsch,et al.  A Survey of Design Transformation Techniques , 1999 .

[13]  Dennis Tsichritzis,et al.  The Equivalence Problem of Simple Programs , 1970, JACM.

[14]  Wuu Yang,et al.  Detecting Program Components With Equivalent Behaviors , 1989 .

[15]  Patrick Cousot,et al.  Verification of Embedded Software: Problems and Perspectives , 2001, EMSOFT.

[16]  Sreeranga P. Rajan,et al.  From VHDL to efficient and first-time-right designs: a formal approach , 1996, TODE.

[17]  George C. Necula,et al.  Translation validation for an optimizing compiler , 2000, PLDI '00.

[18]  Utpal Banerjee,et al.  Loop Transformations for Restructuring Compilers: The Foundations , 1993, Springer US.

[19]  Richard Gerber,et al.  Symbolic Model Checking of Infinite State Systems Using Presburger Arithmetic , 1997, CAV.

[20]  Derek C. Oppen,et al.  A 2^2^2^pn Upper Bound on the Complexity of Presburger Arithmetic , 1978, J. Comput. Syst. Sci..

[21]  Amir Pnueli,et al.  Translation Validation: From SIGNAL to C , 1999, Correct System Design.

[22]  F. Catthoor,et al.  System level verification of video and image processing specifications , 1995 .