Advanced 3D mixed-signal processor for infrared focal plane arrays: Fabrication and test

We report successful implementation of high-density 3D integration technology in the fabrication of advanced mixed-signal processors for infrared focal plane arrays. Separate analog and digital integrated circuits (ICs) were custom designed and fabricated in standard bulk CMOS technology in two different commercial foundries. The 3D interconnects were arrayed in a 256×256 format with a 30 micron pitch and had the form of through-silicon vias 4 micron in diameter and 30 micron deep. Completed 3D readout IC stacks were tested pixel by pixel, demonstrating operability of 99.9%. The 3D IC stacks were hybridized with infrared photodiode arrays and produced functional FPA imagers with 99.9% array operability and unprecedented performance. Such imaging arrays and other smart sensors enabled by 3D integration of sensing elements with sophisticated signal processing are of increasing interest for Internet-of-Things applications, from net-enabled surveillance to mobile health.

[1]  Douglas C. Oakley,et al.  Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits , 2009, 2009 IEEE International Conference on 3D System Integration.

[2]  C. Bower,et al.  High Density 3-D Integration Technology for Massively Parallel Signal Processing in Advanced Infrared Focal Plane Array Sensors , 2006, 2006 International Electron Devices Meeting.

[3]  Joel Silberman,et al.  A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias , 2012, 2012 IEEE International Solid-State Circuits Conference.

[4]  Stuart Horn,et al.  Progress in the development of vertically integrated sensor arrays (Invited Paper) , 2005, SPIE Defense + Commercial Sensing.

[5]  Philip G. Emma,et al.  Is 3D chip technology the next growth engine for performance improvement? , 2008, IBM J. Res. Dev..

[6]  E. Dereniak,et al.  Infrared Detectors and Systems , 1996 .

[7]  Vyshnavi Suntharalingam,et al.  Laser Radar Imager Based on 3D Integration of Geiger-Mode Avalanche Photodiodes with Two SOI Timing Circuit Layers , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[8]  R. Berger,et al.  Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[9]  C.K. Chen,et al.  A wafer-scale 3-D circuit integration technology , 2006, IEEE Transactions on Electron Devices.

[10]  D. Malta,et al.  Bonding for 3-D Integration of Heterogeneous Technologies and Materials , 2008, ECS Transactions.

[11]  Peter D. Dreiske.  Development of two-color focal-plane arrays based on HDVIP (Invited Paper) , 2005, SPIE Defense + Commercial Sensing.

[12]  L. Ratti,et al.  Radiation Tolerance of Devices and Circuits in a 3D Technology Based on the Vertical Integration of Two 130-nm CMOS Layers , 2013, IEEE Transactions on Nuclear Science.