SAT-Based Logic Optimization and Resynthesis

The paper develops a technology-independent optimization and post-mapping resynthesis for combinational logic networks, with emphasis on scalability and optimizing power. The proposed resynthesis (a) is capable of substantial logic restructuring, (b) is customizable to solve a variety of optimization tasks, and (c) has reasonable runtime on large industrial designs. The approach is based on several heterogeneous algorithms, which include structural analysis, random and constrained simulation, and manipulation of Boolean functions using a SAT solver. Structural methods include improved windowing, which focuses on reconvergent logic structures rich in functional flexibilities. It is shown how a mainstream SAT solver can be minimally modified by combining it with an interpolation package, which computes Boolean functions of nodes after resynthesis as a by-product of completed feasibility proofs. Experimental results focusing on the minimization of the number of 6-LUTs after high-effort iterative FPGA mapping with structural choices, demonstrate that the proposed resynthesis, applied to 15 benchmarks reduced area by 6.0% and delay by 2.3% on average. For 5 benchmarks derived from PLA descriptions, the reduction of 5x in area and 20% in depth was obtained, which speaks for the powerful nature of Boolean optimization employed in the proposed resynthesis.