Use of COTS microelectronics in radiation environments

This paper addresses key issues for the cost-effective use of COTS (Commercially available Off The Shelf) microelectronics in radiation environments that enable circuit or system designers to manage risks and ensure mission success. We review several factors and tradeoffs affecting the successful application of COTS parts including (1) hardness assurance and qualification issues; (2) system hardening techniques, and (3) life-cycle costs. The paper also describes several experimental studies that address trends in total-dose, transient, and single-event radiation hardness as COTS technology scales to smaller feature sizes. As an example, the level at which dose-rate upset occurs in Samsung SRAMs increases from 1.4/spl times/10/sup 8/ rad(Si)/s for a 256 K SRAM to 7.7/spl times/10/sup 9/ rad(Si)/s for a 4 M SRAM, indicating unintentional hardening improvements in the design or process of a commercial technology. Additional experiments were performed to quantify variations in radiation hardness for COTS parts. In one study, only small (10-15%) variations were found in the dose-rate upset and latchup thresholds for Samsung 4 M SRAMs from three different date codes. In another study, irradiations of 4 M SRAMs from Samsung, Hitachi, and Toshiba indicate large differences in total-dose radiation hardness. The paper attempts to carefully define terms and clear up misunderstandings about the definitions of "COTS" and "radiation-hardened (RH)" technology.

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