Technique for determining a prudent voltage stress to improve product quality and reliability

Abstract The use of voltage stressing is a powerful technique for improving quality and reliability of integrated circuits when performed correctly. Determining the safe voltage level to use with a particular device has sometimes been elusive. This paper presents a technique for determining a safe voltage level for voltage stressing of packaged or urrpackaged integrated circuit devices. This technique is based on the observed normal distribution of voltage to fail data collected during product characterization. The paper presents empirical data to verify applicability to a variety of semiconductor devices.