Modeling and Analysis of Gate Line Edge Roughness Effect on CMOS Scaling Towards Deep Nanoscale Gate Length

L. Introduction The line edge roughness (LER) of photoresist patterns may be a serious limiting factor in cMos scaling into the nanometer regime [1] [2], because the current state-of-the-art edge roughness of the gate poly lines is of order of several nanometers (> -5 nm), leading to significant performance fluctuations in the devices with exffemely smalr dimensions. In this work, we have employed two-dimensional simulation approach and the simplified physical modeling for onand off-state current variations to understand and analyze the impact of statistical gate line edge roughness on : (l) the device parameter fluctuations, (Z) the short channel performance associated with minimum gate length, (3) conventional effective channel length exftaction methods such as Shift & Ratio method, and (4) the future CMOS technology generation.