论文信息 - Reliability versus yield and die location in advanced VLSI

Reliability versus yield and die location in advanced VLSI

Abstract The results of multiple correlations between reliability and yield on a die level basis are presented for an advanced microprocessors fabricated using a 0.25μ, five layer metal CMOS logic process. Traceability information was programmed into each unit; investigated were infant mortality of edge die versus center die, effects of unusual sort yield signatures on infant mortality, alternating row effects, and the sources of variability of burn in failures. The model that reliability defect density is proportional to yield defect density was found to be in excellent agreement with experimental data over a wide range of yield values. The x-y die position yield was found to be an excellent predictor of infant mortality. The variation in infant mortality from wafer to wafer was found to be twice the lot to lot variation, consistent with the large number of single wafer processing tools used on advanced fabrication processes. Because the traceability information was part of the standard manufacturing flow this analysis was performed using very large, 1 million unit sample sizes.

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