Boolean decomposition in multilevel logic optimization

Algorithms are presented for Boolean decomposition, which can be used to decompose a programmable logic array (PLA) into a set of smaller interconnected PLAs such that the overall area of the resulting logic network, deemed to be the sum of the areas of the constituent PLAs, is minimized. These algorithms can also be used to identify good Boolean factors which can be used as strong divisors during the logic optimization to reduce the literal counts/area of general multilevel logic networks. Excellent results have been obtained. >

[1]  Robert K. Brayton,et al.  Multi-level logic minimization using implicit don't cares , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Alberto L. Sangiovanni-Vincentelli,et al.  Multiple-Valued Minimization for PLA Optimization , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Robert K. Brayton,et al.  Optimal State Assignment for Finite State Machines , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Robert K. Brayton,et al.  MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  William W. Cohen,et al.  Synthesis and Optimization of Multilevel Logic under Timing Constraints , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Srinivas Devadas,et al.  Topological Optimization of Multiple-Level Array Logic , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Roy A. Wood.  A High Density Programmable Logic Array Chip , 1979, IEEE Transactions on Computers.

[8]  Gary D. Hachtel,et al.  BOLD: The Boulder Optimal Logic Design system , 1989, [1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track.

[9]  Louise Trevillyan,et al.  Logic Synthesis Through Local Transformations , 1981, IBM J. Res. Dev..

[10]  Giovanni De Micheli.  Symbolic Design of Combinational and Sequential Logic Circuits Implemented by Two-Level Logic Macros , 1986, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Tsutomu Sasao.  Application of multiple-valued logic to a serial decomposition of PLAs , 1989, Proceedings. The Nineteenth International Symposium on Multiple-Valued Logic.