Probabilistic delay fault model for DVFS circuits

Decreasing the power supply voltage in dynamic voltage frequency scaling to save power consumption may introduce extra delays in CMOS circuits, which may cause errors. This paper presents the probabilistic delay fault model (PDFM), which describes the probability of an error occurring as a function of the power supply voltage and the clock period in synchronous CMOS circuits. In a wide range of applications (graphic, video, digital filtering, etc.), errors occurring with low probability and not remaining for a long time are acceptable. For combinational circuits which have long critical paths with low probability of excitation, a performance increase is achieved with a certain rate of errors determined by the PDFM compared with the traditional design which considers the worst case. The PDFM applied to array multipliers and ripple carry adders shows the agreement of the predicted probabilities with simulated delay histograms to support the practicality of using the PDFM to select power supply voltage and clock period in dynamic voltage frequency scaling circuits with tolerable error rates.

[1]  Jacob Savir,et al.  Random Pattern Testability of Delay Faults , 1988, IEEE Trans. Computers.

[2]  John J. Shedletsky,et al.  An Experimental Delay Test Generator for LSI Logic , 1980, IEEE Transactions on Computers.

[3]  Manoj Sachdev,et al.  Variation-Aware Adaptive Voltage Scaling System , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[5]  Kwang-Ting Cheng,et al.  Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  David G. Chinnery,et al.  Closing the power gap between ASIC and custom: an ASIC perspective , 2000, Proceedings. 42nd Design Automation Conference, 2005..

[7]  A. R. Newton,et al.  Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .

[8]  Robert A. Rasmussen,et al.  Delay test generation , 1977, DAC '77.

[9]  E. S. Park,et al.  The Total Delay Fault Model and Statistical Delay Fault Coverage , 1992, IEEE Trans. Computers.

[10]  John P. Hayes,et al.  High-level delay test generation for modular circuits , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Naresh R. Shanbhag,et al.  Energy-efficient signal processing via algorithmic noise-tolerance , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[12]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[13]  Kaushik Roy,et al.  Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis , 2010, 2010 15th IEEE European Test Symposium.