An Update Method for a Low Power Cam Emulator Using an LUT Cascade Based on an EVMDD (k)

Core routers perform longest prefix matching (LPM) using content addressable memories (CAMs). With the rapid growth of the Internet, LPM has become the bottleneck in network traffic management. In the previous publication, we have proposed an area-efficient and highperformance CAM emulator using an LUT cascade based on an edgevalued multi-valued decision diagram (EVMDD (k)). In the internet, registered vectors must be updated frequently. In this paper, we propose an algorithm to update an LUT cascade. We implemented the proposed algorithm on the ARM processor. Its update time is shorter than the peak update time of the BGP protocol. Also, we analyzed the power consumption of the LUT cascade with respect to both the static and the dynamic power. Experimental results show that, as for the lookup speed per area and the power consumption, our architecture outperforms existing CAM realizations on FPGAs.

[1]  Nakahara Hiroki,et al.  A CAM Emulator Using Look-Up Table Cascades , 2007 .

[2]  Viktor K. Prasanna,et al.  Scalable Packet Classification on FPGA , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Tsutomu Sasao.  Memory-Based Logic Synthesis , 2011 .

[4]  Tsutomu Sasao.  A cascade realization of multiple-output function for reconfigurable hardware , 2001 .

[5]  Tsutomu Sasao,et al.  Implementation of Multiple-Valued CAM Functions by LUT Cascades , 2006, 36th International Symposium on Multiple-Valued Logic (ISMVL'06).

[6]  Tiziano Villa,et al.  Multi-valued decision diagrams: theory and applications , 1998 .

[7]  Viktor K. Prasanna,et al.  Scalable High Throughput and Power Efficient IP-Lookup on FPGA , 2009, 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines.

[8]  Shinobu Nagayama,et al.  Complexities of Graph-Based Representations for Elementary Functions , 2009, IEEE Transactions on Computers.

[9]  Yung-Te Lai,et al.  Edge-valued binary decision diagrams for multi-level hierarchical verification , 1992, DAC '92.

[10]  Rodney S Tucker.  Optical Packet-Switched WDM Networks: a Cost and Energy Perspective , 2008, OFC/NFOEC 2008 - 2008 Conference on Optical Fiber Communication/National Fiber Optic Engineers Conference.

[11]  Gordon J. Brebner,et al.  Mutable Codesign for Embedded Protocol Processing , 2005, FCCM.

[12]  Tsutomu Sasao,et al.  A packet classifier using LUT cascades based on EVMDDS (k) , 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

[13]  최용석,et al.  Content Addressable Memory의 설계 ( A Design of a Content Addressable Memory ) , 1996 .

[14]  Sofia Cassel,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 2012 .

[15]  Shinobu Nagayama,et al.  Representations of Elementary Functions Using Edge-Valued MDDs , 2007, 37th International Symposium on Multiple-Valued Logic (ISMVL'07).

[16]  Shinobu Nagayama,et al.  Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs , 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[17]  Masahiro Fujita,et al.  Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping , 1997, Formal Methods Syst. Des..

[18]  Tsutomu Sasao,et al.  An Update Method for a CAM Emulator Using an LUT Cascade Based on an EVMDD (K) , 2014, 2014 IEEE 44th International Symposium on Multiple-Valued Logic.