Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires

This paper studies the problems of minimizing power dissipation of an interconnect wire by simultaneously considering buffer insertion/sizing and wire sizing. We obtain optimal solutions for the problems of optimizing power dissipation for simultaneous buffer insertion/sizing and uniform wire sizing (BISUWS) under the delay constraints. These solutions can be used to estimate the power dissipation in the interconnect designs.

[1]  Dian Zhou,et al.  Minimization of chip size and power consumption of high-speed VLSI buffers , 1997, ISPD '97.

[2]  Anantha P. Chandrakasan,et al.  Sources of Power Consumption , 1995 .

[3]  Jason Cong,et al.  An interconnect-centric design flow for nanometer technologies , 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

[4]  Martin D. F. Wong,et al.  A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Jacob K. White,et al.  FastCap: A Multipole Accelerated 3-D Extraction Program , 1991 .

[6]  Eby G. Friedman,et al.  Repeater design to reduce delay and power in resistive interconnect , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[7]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[8]  Wayne Burleson,et al.  A practical approach to DSM repeater insertion: satisfying delay constraints while minimizing area and power , 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).

[9]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[10]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[11]  Jason Cong,et al.  Buffer block planning for interconnect planning and prediction , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[12]  D. F. Wong,et al.  Closed form solutions to simultaneous buffer insertion/sizing and wire sizing , 2001, ACM Trans. Design Autom. Electr. Syst..

[13]  Charles J. Alpert,et al.  Interconnect synthesis without wire tapering , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Daniel Auvergne,et al.  Design and selection of buffers for minimum power-delay product , 1996, Proceedings ED&TC European Design and Test Conference.

[15]  Jason Cong,et al.  Performance optimization of VLSI interconnect layout , 1996, Integr..

[16]  Chung-Kuan Cheng,et al.  Optimal wire sizing and buffer insertion for low power and a generalized delay model , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[17]  Charles J. Alpert,et al.  Wire segmenting for improved buffer insertion , 1997, DAC.

[18]  J.D. Meindl,et al.  Optimal interconnection circuits for VLSI , 1985, IEEE Transactions on Electron Devices.

[19]  Xuan Zeng,et al.  Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing , 2003, ICCAD.

[20]  Anantha P. Chandrakasan,et al.  Low Power Digital CMOS Design , 1995 .

[21]  Chung-Kuan Cheng,et al.  Optimal wire sizing and buffer insertion for low power and a generalized delay model , 1996 .

[22]  Martin D. F. Wong,et al.  Closed form solution to simultaneous buffer insertion/sizing and wire sizing , 1997, ISPD '97.

[23]  J. Cong,et al.  Optimal wiresizing under the distributed Elmore delay model , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[24]  Kaustav Banerjee,et al.  A power-optimal repeater insertion methodology for global interconnects in nanometer designs , 2002 .

[25]  J. Cong,et al.  Interconnect design for deep submicron ICs , 1997, ICCAD 1997.