A 285-MHz Pipelined MAP Decoder in 0 . 18-m CMOS

Presented in this paper is a pipelined 285-MHz maximum a posteriori probability (MAP) decoder IC. The 8.7-mm IC is implemented in a 1.8-V 0.18m CMOS technology and consumes 330 mW at maximum frequency. The MAP decoder chip features a block-interleaved pipelined architecture, which enables the pipelining of the add-compare-select kernels. Measured results indicate that a turbo decoder based on the presented MAP decoder core can achieve: 1) a decoding throughput of 27.6 Mb/s with an energy-efficiency of 2.36 nJ/b/iter; 2) the highest clock frequency compared to existing 0.18m designs with the smallest area; and 3) comparable throughput with an area reduction of 3-4 3 with reference to a look-ahead based high-speed design (Radix-4 design), and a parallel architecture.

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