Error-Correcting Code Aware Memory Subsystem

An error-correcting code (ECC) immune to bit errors has been widely used in reliable computer systems. However, ECC techniques can make memory performance severely degraded since incomplete-word write requests lead to inefficient read-to-write (RTW) and write-to-read operations of synchronous dynamic random access memory. In this paper, we propose a memory subsystem efficient for ECC operations. Our key idea is that the RTW operations causing incomplete-word write requests are split and grouped into independent read and write operations, and then the grouped read and write operations are individually scheduled for the optimal memory performance under application constraints. Experimental results show that the proposed ECC-aware memory subsystem achieves 17% shorter memory latency, and 12% higher memory utilization, on average, than the latest conventional memory subsystems on industrial multimedia applications. Moreover, the ECC-aware memory subsystem improves up to 2.5 times higher memory performance on synthetic benchmarks.

[1]  Lizy Kurian John,et al.  Minimalist open-page: A DRAM page-mode scheduling policy for the many-core era , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[2]  Gary J. Sullivan,et al.  Rate-constrained coder control and comparison of video coding standards , 2003, IEEE Trans. Circuits Syst. Video Technol..

[3]  David Z. Pan,et al.  An SDRAM-Aware Router for Networks-on-Chip , 2010, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Woo-Young Jang.  DECO: DIMM controller efficient for ECC operations , 2014 .

[5]  David Z. Pan,et al.  Application-Aware NoC Design for Efficient SDRAM Access , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  David Z. Pan,et al.  An SDRAM-aware router for Networks-on-Chip , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[7]  Eduardo Pinheiro,et al.  DRAM errors in the wild: a large-scale field study , 2009, SIGMETRICS '09.

[8]  Long Chen,et al.  Pre-Read and Write-Leak Memory Scheduling Algorithm , 2012 .

[9]  Eric Bogatin.  Signal Integrity - Simplified , 2003 .

[10]  Lizy Kurian John,et al.  The virtual write queue: coordinating DRAM and last-level cache policies , 2010, ISCA.

[11]  Gary J. Sullivan,et al.  Overview of the High Efficiency Video Coding (HEVC) Standard , 2012, IEEE Transactions on Circuits and Systems for Video Technology.

[12]  Norman P. Jouppi,et al.  Staged Reads: Mitigating the impact of DRAM writes on DRAM reads , 2012, IEEE International Symposium on High-Performance Comp Architecture.

[13]  Calvin Lin,et al.  Memory scheduling for modern microprocessors , 2007, TOCS.

[14]  Onur Mutlu,et al.  DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems , 2010 .

[15]  Ajay Luthra,et al.  Overview of the H.264/AVC video coding standard , 2003, IEEE Trans. Circuits Syst. Video Technol..