Simulation-based high-level synthesis of Nyquist-rate data converters using MATLAB/SIMULINK

This paper presents a toolbox for the simulation, optimization and high-level synthesis of Nyquist-rate Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters in MATLAB. The embedded simulator uses SIMULINK C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time up to 2 orders of magnitude as compared with previous approaches - based on the use of SIMULINK elementary blocks. Moreover, S-functions are more suitable for implementing a more detailed description of the circuit. For all subcircuits, the accuracy of the behavioral models has been verified by electrical simulation using HSPICE. For synthesis purposes, the simulator is used for performance evaluation and combined with an hybrid optimizer for design parameter selection. The optimizer combines adaptive statistical optimization algorithm inspired in simulated annealing with a design-oriented formulation of the cost function. It has been integrated in the MATLAB/SIMULINK platform by using the MATLAB engine library, so that the optimization core runs in background while MATLAB acts as a computation engine. The implementation on the MATLAB platform brings numerous advantages in terms of signal processing, high flexibility for tool expansion and simulation with other electronic subsystems. Additionally, the presented toolbox comprises a friendly graphical user interface to allow the designer to browse through all steps of the simulation, synthesis and post-processing of results. In order to illustrate the capabilities of the toolbox, a 0.13μm CMOS 12-bit@80MS/s analog front-end for broadband power line communications, made up of a pipeline ADC and a current steering DAC, is synthesized and high-level sized. Different experiments show the effectiveness of the proposed methodology.

[1]  Alberto L. Sangiovanni-Vincentelli,et al.  Verification of Nyquist data converters using behavioral simulation , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Luis Hernandez,et al.  Oversampled pipeline A/D converters with mismatch shaping , 1998 .

[3]  Ángel Rodríguez-Vázquez,et al.  Top-Down Design of High-Performance Sigma-Delta Modulators , 1998 .

[4]  Georges Gielen,et al.  A 14b 150Msamples/s update rate Q2 random walk CMOS DAC , 1999 .

[5]  W. Sansen,et al.  SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters , 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

[6]  Howard C. Luong,et al.  Power optimization for pipeline analog-to-digital converters , 1999 .

[7]  J. Jacob Wikner,et al.  CMOS Data Converters for Communications , 2000 .

[8]  Randall L. Geiger,et al.  Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays , 2000 .

[9]  W. Sansen,et al.  A high-performance multibit /spl Delta//spl Sigma/ CMOS ADC , 2000, IEEE Journal of Solid-State Circuits.

[10]  Rob A. Rutenbar,et al.  Computer-aided design of analog and mixed-signal integrated circuits , 2000, Proceedings of the IEEE.

[11]  Michiel Steyaert,et al.  A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter , 2001 .

[12]  L. Singer,et al.  A 3 V 340 mW 14 b 75 MSPS CMOS ADC with 85 dB SFDR at Nyquist , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[13]  F. Maloberti,et al.  Behavioral model of pipeline ADC by using SIMULINK(R) , 2001, 2001 Southwest Symposium on Mixed-Signal Design (Cat. No.01EX475).

[14]  J. C. Vital Systematic design for optimization of pipelined ADCs [Book Review] , 2001, IEEE Circuits and Devices Magazine.

[15]  K. Uyttenhove,et al.  A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS , 2003, IEEE J. Solid State Circuits.

[16]  Michiel Steyaert,et al.  Systematic Design of Analog IP Blocks , 2003 .

[17]  Michiel Steyaert,et al.  Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter , 2003 .

[18]  Fernando Medeiro,et al.  CMOS telecom data converters , 2003 .

[19]  John D. Hyde,et al.  A 300-MS/s 14-bit digital-to-analog converter in logic CMOS , 2003, IEEE J. Solid State Circuits.

[20]  O. Shoaei,et al.  Systematic design for power minimization of pipelined analog-to-digital converters , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[21]  A. Wiesbauer,et al.  A 15 MHz bandwidth sigma-delta ADC with 11 bits of resolution in 0.13/spl mu/m CMOS , 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).